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US 11,907,528 B2Granted
Multi-processor bridge with cache allocate awareness
AssigneeTexas Instruments Incorporated
InventorsKai Chirca, Daniel Wu, Matthew David Pierson
Life of this patent
Estimating the term…
Abstract
Techniques for loading data, comprising receiving a memory management command to perform a memory management operation to load data into the cache memory before execution of an instruction that requests the data, formatting the memory management command into one or more instruction for a cache controller associated with the cache memory, and outputting an instruction to the cache controller to load the data into the cache memory based on the memory management command.
Claims20
A processing system comprising:
- a plurality of processors including a first processor;
- a cache memory coupled to the plurality of processors;
- and
- a shared memory controller comprising:
- circuitry configured to receive a memory management command having a specification to perform a memory management operation to load data into a memory location of the cache memory before the first processor executes an input/output instruction that requests the data from the memory location;
- formatting circuitry configured to format the memory management command into a formatted command;
- and
- routing circuitry configured to route the formatted command based on the specification;
- and
- response circuitry configured to receive a response indicating the data was loaded into the memory location.
7 more elements
A method comprising:
- receiving, by a shared memory controller, a memory management command having a specification to perform a memory management operation to load data into a memory location of a cache memory before a first processor of a plurality of processors executes an input/output instruction that requests the data from the memory location;
- formatting, by formatting circuitry, the memory management command into a formatted command;
- routing, by routing circuitry, the formatted command based on the specification;
- receiving, by response circuitry, a response indicating the data was loaded into the memory location.
1 more element
A processing system comprising:
- a plurality of processors including a first processor and a second processor, wherein the second processor includes a memory interface;
- a cache memory coupled to the plurality of processors;
- a bridge circuit, wherein the second processor is coupled to the cache memory by the bridge circuit;
- and
- a shared memory controller comprising:
- circuitry configured to receive a memory management command having a specification to perform a memory management operation to load data into a memory location of the cache memory before the first processor executes an input/output instruction that requests the data from the memory location;
- formatting circuitry configured to format the memory management command into a formatted command;
- and
- routing circuitry configured to route the formatted command based on the specification to the bridge circuit;
- and
- response circuitry configured to receive a first response from the bridge circuit,
- wherein the bridge circuit is configured to:
- translate the formatted command into an op code;
- transmit the op code to the memory interface of the second processor;
- receive a second response from the second processor indicating the data was loaded into the memory location;
- and
- send the first response to the response circuitry indicating the data was loaded into the memory location.
14 more elements
Dependencies are inferred from the claim text.