Low latency matrix multiply unit
AssigneeGoogle Inc.
InventorsAndrew Everett Phelps, Norman Paul Jouppi
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AssigneeGoogle Inc.
InventorsAndrew Everett Phelps, Norman Paul Jouppi
Estimating the term…
Methods, systems, and apparatus for a matrix multiply unit implemented as a systolic array of cells are disclosed. Each cell of the matrix multiply includes: a weight matrix register configured to receive a weight input from either a transposed or a non-transposed weight shift register; a transposed weight shift register configured to receive a weight input from a horizontal direction to be stored in the weight matrix register; a non-transposed weight shift register configured to receive a weight input from a vertical direction to be stored in the weight matrix register; and a multiply unit that is coupled to the weight matrix register and configured to multiply the weight input of the weight matrix register with a vector data input in order to obtain a multiplication result.
A processor comprising:
A method performed by a core of one or more cores included in a processor, the method comprising:
A non-transitory computer program product storing instructions that, when executed by a core of one or more cored included in a programmable processor, cause the core to perform operations comprising:
Dependencies are inferred from the claim text.