US 11,907,160 B2 · Distributed processor system

Abstract

This disclosure relates to a distributed processing system for configuring multiple processing channels. The distributed processing system includes a main processor, such as an ARM processor, communicatively coupled to a plurality of co-processors, such as stream processors. The co-processors can execute instructions in parallel with each other and interrupt the ARM processor. Longer latency instructions can be executed by the main processor and lower latency instructions can be executed by the co-processors. There are several ways that a stream can be triggered in the distributed processing system. In an embodiment, the distributed processing system is a stream processor system that includes an ARM processor and stream processors configured to access different register sets. The stream processors can include a main stream processor and stream processors in respective transmit and receive channels. The stream processor system can be implemented in a radio system to configure the radio for operation.

Claims16

Dependent claims

A stream processing system for configuring multiple processing channels, the stream processing system comprising:

a main stream processor;
and
a plurality of processing channels comprising:
a first processing channel comprising first registers and a first stream processor, the first stream processor configured to receive a first trigger from the main stream processor that causes the first stream processor to execute a first set of instructions that include at least one instruction to access at least one of the first registers;
and
a second processing channel comprising second registers and a second stream processor, the second stream processor configured to receive a second trigger from the main stream processor that causes the second stream processor to execute a second set of instructions that include at least one instruction to access at least one of the second registers, wherein the second stream processor is configured to trigger a stream in the main stream processor to access one or more of the first registers of the first processing channel, and wherein the first stream processor and the second stream processor are programmable.

3 more elements

Dependencies are inferred from the claim text.

Distributed processor system

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Distributed processor system

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Abstract

Claims16