Latency and power efficient clock and data recovery in a high-speed one-wire bidirectional bus

A method of data communication, comprising:

• configuring an oscillator to generate a base clock signal with a base frequency;
• configuring a clock gating circuit to output a gated base clock signal while the clock gating circuit is enabled, the clock gating circuit being responsive to one or more control inputs;
• configuring a first counter to provide a counter output that reflects a count of positive and negative edges in the gated base clock signal that clocks the first counter;
• configuring control logic to disable the clock gating circuit when the counter output corresponds to a maximum count value;
• and
• configuring an edge synchronization circuit to:
• ignore edges in a signal received by the edge synchronization circuit from a one-wire bus while the counter output has a value that is less than the maximum count value;
• and
• reset the first counter in response to an edge detected in the signal received from the one-wire bus.

A data communication apparatus, comprising:

• means for generating a base clock signal with a base frequency;
• means for gating the base clock signal, including a clock gating circuit responsive to one or more control inputs, the means for gating the base clock signal being configured to output a gated base clock signal while the clock gating circuit is enabled;
• means for counting positive and negative edges in the gated base clock signal, including a first counter clocked by the gated base clock signal;
• means for disabling the clock gating circuit, including control logic coupled to a first control input of the clock gating circuit, the means for disabling the clock gating circuit being configured to disable the clock gating circuit when an output of the first counter corresponds to a maximum count value;
• and
• means for synchronizing the means for counting positive and negative edges in the signal received from a one-wire bus, configured to:
• ignore edges in the signal received from the one-wire bus while the output of the first counter represents a value that is less than the maximum count value;
• and
• reset the first counter in response to an edge detected in the signal received from the one-wire bus.

A non-transitory processor-readable storage medium storing code thereon, the code when executed by a processor in a processing circuit causes the processing circuit to:

• configure an oscillator to generate a base clock signal with a base frequency;
• configure a clock gating circuit to output a gated base clock signal while the clock gating circuit is enabled, the clock gating circuit being responsive to one or more control inputs;
• configure a first counter to provide a counter output that reflects a count of positive and negative edges in the gated base clock signal that clocks the first counter;
• configure control logic to disable the clock gating circuit when the counter output corresponds to a maximum count value;
• and
• configure an edge synchronization circuit to:
• ignore edges in a signal received by the edge synchronization circuit from a one-wire bus while the counter output has a value that is less than the maximum count value;
• and
• reset the first counter in response to an edge detected in the signal received from the one-wire bus.