Reconfigurable server and server rack with same

A reconfigurable server, comprising:

• main memory;
• a processor module with a processor array, the processor array connected to the main memory and having a plurality of peripheral interconnect channels supporting a first communication protocol that is serial and a plurality of high data rate capable channels supporting a second communication protocol different than the first communication protocol;
• a hardware plane module with a first programmable logic device (PLD) that is a field programmable gate array (FPGA), the first PLD connected to the plurality of high data rate capable channels, and
• a plurality of near-memory accelerator modules connected to the first PLD, each of the near-memory accelerator modules having a second PLD, wherein the second PLD is connected to the first PLD and each of the second PLDs is connected to a peripheral interconnect switch with a predetermined number of peripheral interconnect lanes, each of the peripheral interconnect switches being connected to a near-memory module with the predetermined number of PCie lanes, wherein a bandwidth between the second PLD and the corresponding near-memory module is only within ten percent of a bandwidth between the second PLD and the first PLD.

A server rack, comprising:

• main memory;
• a switch;
• and
• a plurality of servers connected to the switch, at least one of the servers being a reconfigurable server that comprises:
• a processor module with a processor array, the processor array connected to the main memory and having a plurality of peripheral interconnect channels supporting a first communication protocol that is serial and a plurality of high data rate capable channels supporting a second communication protocol different than the first communication protocol;
• a hardware plane module with a first programmable logic device (PLD) that is a field programmable gate array (FPGA), the first PLD connected to the plurality of high data rate capable channels, wherein the hardware plane module comprises a connector array connected to the first PLD, the connector array comprising a plurality of connectors configured to be connected to external devices, and a plurality of near-memory accelerator modules connected to the first PLD, each of the near-memory accelerator modules having a second PLD, wherein the second PLD is connected the first PLD and each of the second PLDs is connected to a peripheral interconnect switch with a predetermined number of peripheral interconnect lanes, each of the peripheral interconnect switches being connected to a near-memory module with the predetermined number of peripheral interconnect lanes,
• wherein a bandwidth between the second PLD and the corresponding near-memory module is only within ten percent of a bandwidth between the second PLD and the first PLD;
• wherein at least one of the other plurality of servers is connected to the hardware plane module via one of the plurality of connectors.