Integrated circuit device with multiple direct memory access (DMA) data paths

A system comprising:

• a source device;
• a target device;
• a first data path coupled between the source device and the target device, wherein the first data path is a blocking data path and includes:
• a first interconnect segment coupled to the source device;
• a second interconnect segment coupled to the target device;
• and
• a bridge circuit coupled between the first interconnect segment and the second interconnect segment;
• a first direct memory access (DMA) circuit coupled to the source device;
• a second DMA circuit coupled to the target device;
• and
• a second data path coupled between the first DMA circuit and the second DMA circuit, wherein the second data path is a non-blocking data path.

A device comprising:

• a first data path configured to couple between a source device and a target device, wherein the first data path is a blocking data path and includes:
• a first interconnect segment coupled to the source device;
• a second interconnect segment coupled to the target device;
• and
• a bridge circuit coupled between the first interconnect segment and the second interconnect segment;
• a first direct memory access (DMA) circuit configured to couple to the source device;
• a second DMA circuit configured to couple to the target device;
• and
• a second data path coupled between the first DMA circuit and the second DMA circuit, wherein the second data path is a non-blocking data path.