US 11,907,141 B1 · Flexible dual ranks memory system to boost performance

Abstract

Various embodiments include methods for implementing flexible ranks in a memory system. Embodiments may include receiving, at a memory controller, a first memory access command and a first address at which to implement the first memory access command in a logical rank, generating, by the memory controller, a first signal configured to indicate to a first memory device of the logical rank to implement the first memory access command via a first partial channel, sending, from the memory controller, the first signal to the first memory device, generating, by the memory controller, a second signal configured to indicate to a second memory device of the logical rank that is different from the first memory device to implement the first memory access command via a second partial channel, and sending, from the memory controller, the second signal to the second memory device.

Claims27

Dependent claims

A method implemented in a memory system, comprising:

receiving, at a memory controller, a first memory access command and a first address at which to implement the first memory access command in a logical rank;
generating, by the memory controller, a first signal configured to indicate to a first memory device of the logical rank to implement the first memory access command via a first partial channel;
sending, from the memory controller, the first signal to the first memory device;
generating, by the memory controller, a second signal configured to indicate to a second memory device of the logical rank that is different from the first memory device to implement the first memory access command via a second partial channel;
and
sending, from the memory controller, the second signal to the second memory device;
and
determining whether the first address at which to implement the first memory access command in the logical rank is at the logical rank,
wherein generating the first signal, sending the first signal, generating the second signal, and sending the second signal occur in response to determining that the first address at which to implement the first memory access command in the logical rank is at the logical rank.

6 more elements

A computing device, comprising:

a first memory device;
a second memory device;
and
a memory controller communicatively connected to the first memory device and the second memory device, and configured to:
receive a first memory access command and a first address at which to implement the first memory access command in a logical rank;
generate a first signal configured to indicate to the first memory device of the logical rank to implement the first memory access command via a first partial channel;
send the first signal to the first memory device;
generate a second signal configured to indicate to the second memory device of the logical rank that is different from the first memory device to implement the first memory access command via a second partial channel;
and
send the second signal to the second memory device.

7 more elements

A computing device, comprising:

means for receiving a first memory access command and a first address at which to implement the first memory access command in a logical rank;
means for generating a first signal configured to indicate to a first memory device of the logical rank to implement the first memory access command via a first partial channel;
means for sending the first signal to the first memory device;
means for generating a second signal configured to indicate to a second memory device of the logical rank that is different from the first memory device to implement the first memory access command via a second partial channel;
means for sending the second signal to the second memory device;
and
means for determining whether the first address at which to implement the first memory access command in the logical rank is at the logical rank,
wherein means for generating the first signal, means for sending the first signal, means for generating the second signal, and means for sending the second signal are implemented in response to determining that the first address at which to implement the first memory access command in the logical rank is at the logical rank.

5 more elements

A memory controller configured to:

receive a first memory access command and a first address at which to implement the first memory access command in a logical rank;
generate a first signal configured to indicate to a first memory device of the logical rank to implement the first memory access command via a first partial channel;
send the first signal to the first memory device;
generate a second signal configured to indicate to a second memory device of the logical rank that is different from the first memory device to implement the first memory access command via a second partial channel;
and
send the second signal to the second memory device;
and
determine whether the first address at which to implement the first memory access command in the logical rank is at the logical rank;
and
generate the first signal, sending the first signal, generate the second signal, and send the second signal occur in response to determining that the first address at which to implement the first memory access command in the logical rank is at the logical rank.

7 more elements

A method implemented in a memory system, comprising:

receiving, at a first partial channel interface of a first memory device for a first partial channel, a first refresh signal;
receiving, at a second partial channel interface of a second memory device for a second partial channel, a second refresh signal;
implementing, via the first partial channel, a refresh operation at the first memory device in response to the first refresh signal;
and
implementing, via the second partial channel, a refresh operation at the second memory device in response to the second refresh signal.

2 more elements

Dependencies are inferred from the claim text.

Flexible dual ranks memory system to boost performance

Life of this patent

Flexible dual ranks memory system to boost performance

Life of this patent

Abstract

Claims27