Memory system design using buffer(s) on a mother board

A system comprising:

• a processor comprising a memory controller;
• a first data buffer device;
• a first memory channel coupled between the processor and the first data buffer device;
• and
• a dual in-line memory module (DIMM) coupled to the first data buffer device via a second memory channel and a third memory channel, wherein the DIMM comprises a second data buffer device coupled to the first data buffer device via the second memory channel and a third data buffer device coupled to the first data buffer device via the second memory channel, wherein the second data buffer device is to access a first rank of one or more memory devices of the DIMM via the second memory channel and the third data buffer device is to access a second rank of one or more memory devices of the DIMM via the third memory channel.

A system comprising:

• a central processing unit (CPU);
• at least one dual in-line memory module (DIMM) comprising a first data buffer device coupled to a first rank of one or more memory devices and a second data buffer device coupled to a second rank of one or more memory devices;
• and
• means for accessing the first rank of the one or more memory devices via a first memory channel;
• means for accessing the second rank of the one or more memory devices via a second memory channel;
• and
• means for sending or receiving data between the CPU and the DIMM via a third memory channel.