Processor with multiple op cache pipelines

A method comprising:

• in response to a identifying a branch prediction at a processor:
• selecting one of a plurality of op cache pipelines of the processor based on the branch prediction and at least two quality of service levels, including at least one quality of service level of a thread being processed by at least one of the plurality of op cache pipelines, each of the plurality of op cache pipelines associated with a different read port of an op cache of the processor, wherein the op cache pipelines provide decoded instructions to op cache entries;
• and
• providing a set of operations associated with the branch prediction to a dispatch stage of the processor via the selected op cache pipeline.

A processor comprising:

• a branch predictor to generate a first branch prediction;
• a dispatch queue;
• a plurality of op cache pipelines, wherein the op cache pipelines provide decoded instructions to op cache entries;
• a control module to select a first op cache pipeline of the plurality of op cache pipelines of the processor, wherein the control module is to select the first op cache pipeline based on operation flow criteria associated with the plurality of op cache pipelines, and wherein the operation flow criteria specify selecting the first op cache pipeline based on at least two quality of service levels, including at least one quality of service level of a thread being processed by at least one of the plurality of op cache pipelines;
• and
• wherein the selected op cache pipeline is to provide operations associated with the first branch prediction to the dispatch queue.