US 11,907,114 B2Granted

Devices, systems, and methods for dynamically remapping memory addresses

AssigneeSmart Iops, Inc.

InventorsAshutosh Kumar Das, Manuel Antonio d'Abreu

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Abstract

In certain aspects, dynamic remapping of memory addresses is provided and includes initiating a remapping of a logical block from a “mapped block” to a “remapped block.” Logical address locations for the logical block are mapped to physical address locations in the mapped block. The mapped and remapped blocks include non-volatile memory. A read command is received and determined to be for reading from a logical address location of the logical block, and the logical address location is determined to be mapped to a physical address location. Data is read from the physical address location of the mapped block. A write command is received and determined to be for writing data to the logical address location. Data is written to the physical address location of the remapped block. The read command is received after the initiation of the remapping and before the writing of the data to the remapped block.

Claims20

Dependent claims

A data storage system, comprising:

non-volatile memory;
and
one or more controllers coupled to the non-volatile memory, the one or more controllers configured to:
map a first logical block to a mapped block so that a plurality of logical address locations for the first logical block are mapped to a first plurality of physical address locations in the mapped block;
receive and execute instructions to initiate and perform a remapping process of the first logical block from the mapped block to a remapped block, the remapping process remapping the plurality of logical address locations to a second plurality of physical address locations in the remapped block,
wherein the non-volatile memory comprises the mapped block and the remapped block,
wherein the remapping process is complete when the plurality of logical address locations are remapped to the second plurality of physical address locations, and
wherein, for each logical address location in the plurality of logical address locations, the instructions, which when executed by the one or more controllers, cause the one or more controllers to:
when a write command for the corresponding logical address location is first received by the one or more controllers during the remapping process and is a first-occurring write command for the corresponding logical address location during the remapping process, perform a corresponding initial write in the remapped block and indicate the corresponding logical address location as remapped;
when a read command for the corresponding logical address location is received by the one or more controllers during the remapping process and before the corresponding logical address location is indicated as remapped, perform a corresponding read in the mapped block;
and
when a read command for the corresponding logical address location is received by the one or more controllers during the remapping process and after the corresponding logical address location is indicated as remapped, perform a corresponding read in the remapped block;
receive a first read command during the remapping process;
determine that the first read command is for reading from a first logical address location of the first logical block;
determine that the first logical address location is mapped to a first physical address location of the plurality of physical address locations;
read first data from the first physical address location of the mapped block;
receive a first write command during the remapping process;
determine that the first write command is for an initial write of second data to the first logical address location of the first logical block;
and
write the second data to a first one of the second plurality of physical address locations of the remapped block;
wherein the receiving of the first read command occurs at a time:
after the initiating of the remapping process of the first logical block;
and
before the writing of the second data to the first physical address location of the remapped block.

21 more elements

A method for dynamically remapping memory addresses in a data storage system, the method comprising:

mapping, by one or more controllers configured to couple to non-volatile memory, a first logical block to a mapped block so that a plurality of logical address locations for the first logical block are mapped to a first plurality of physical address locations in the mapped block;
receiving and executing, by the one or more controllers, instructions to initiate and perform a remapping process of the first logical block from the mapped block to a remapped block, the remapping process remapping the plurality of logical address locations to a second plurality of physical address locations in the remapped block,
wherein the non-volatile memory comprises the mapped block and the remapped block,
wherein the remapping process is complete when the plurality of logical address locations are remapped to the second plurality of physical address locations, and
wherein, for each logical address location in the plurality of logical address locations, the instructions, which when executed by the one or more controllers, cause the one or more controllers to:
when a write command for the corresponding logical address location is first received during the remapping process and is a first occurring write command for the corresponding logical address location during the remapping process, perform a corresponding initial write in the remapped block and indicate the corresponding logical address location as remapped;
when a read command for the corresponding logical address location is received during the remapping process and before the corresponding logical address location is indicated as remapped, perform a corresponding read in the mapped block;
and
when a read command for the corresponding logical address location is received during the remapping process and after the corresponding logical address location is indicated as remapped, perform a corresponding read in the remapped block;
receiving a first read command during the remapping process;
determining that the first read command is for reading from a first logical address location of the first logical block;
determining that the first logical address location is mapped to a first physical address location of the plurality of physical address locations;
reading first data from the first physical address location of the mapped block;
receiving a first write command during the remapping process;
determining that the first write command is for an initial write of second data to the first logical address location of the first logical block;
and
writing the second data to a first one of the second plurality of physical address locations of the remapped block;
wherein the receiving of the first read command occurs at a time:
after the initiating of the remapping process of the first logical block;
and
before the writing of the second data to the first physical address location of the remapped block.

18 more elements

A non-transitory machine-readable storage medium storing machine-executable instructions that, when executed, cause a system to perform a method for dynamically remapping memory addresses, the method comprising:

mapping, by one or more controllers configured to couple to non-volatile memory, a first logical block to a mapped block so that a plurality of logical address locations for the first logical block are mapped to a first plurality of physical address locations in the mapped block;
receiving and executing, by the one or more controllers, instructions to initiate and perform a remapping process of the first logical block from the mapped block to a remapped block, the remapping process remapping the plurality of logical address locations to a second plurality of physical address locations in the remapped block,
wherein the non-volatile memory comprises the mapped block and the remapped block,
wherein the remapping process is complete when the plurality of logical address locations are remapped to the second plurality of physical address locations, and
wherein, for each logical address location in the plurality of logical address locations, the instructions, which when executed by the one or more controllers, cause the one or more controllers to:
when a write command for the corresponding logical address location is received during the remapping process and is a first occurring write command for the corresponding logical address location during the remapping process, perform a corresponding initial write in the remapped block and indicate the corresponding logical address location as remapped;
when a read command for the corresponding logical address location is received during the remapping process and before the corresponding logical address location is indicated as remapped, perform a corresponding read in the mapped block;
and
when a read command for the corresponding logical address location is received during the remapping process and after the corresponding logical address location is indicated as remapped, perform a corresponding read in the remapped block;
receiving a first read command during the remapping process;
determining that the first read command is for reading from a first logical address location of the first logical block;
determining that the first logical address location is mapped to a first physical address location of the plurality of physical address locations;
reading first data from the first physical address location of the mapped block;
receiving a first write command during the remapping process;
determining that the first write command is for an initial write of second data to the first logical address location of the first logical block;
and
writing the second data to a first one of the second plurality of physical address locations of the remapped block;
wherein the receiving of the first read command occurs at a time:
after the initiating of the remapping process of the first logical block;
and
before the writing of the second data to the first physical address location of the remapped block.

18 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/996,810Filed 18 Aug 2020 · us provisional application
Priority: 18 Aug 2019
Published: US 2021/0049094 A118 Feb 2021
Granted: 20 Feb 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

G06F 12/0246
Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory: in block erasable memory, e.g. flash memory
G06F 12/0873
For peripheral storage systems, e.g. disk cache: mapping of cache memory to specific storage devices or parts thereof
G06F 12/1045
Using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]: associated with a data cache
G06F 13/1668
For access to memory bus: details of memory controller

Family

Application62/888,507Us provisional application · filed 18 Aug 2019
US 2021/0049094 A1Pre-grant publication · published 18 Feb 2021
US 11,907,114 B2This patent

From the US filing history. Foreign family members aren’t listed.

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