Generation of trace messages including an instruction retirement count and a stall count
AssigneeSiemens Industry Software Inc.
InventorIain Robertson
Life of this patent
Estimating the term…
Abstract
A method of tracing instruction execution on a processor of an integrated circuit chip in real time whilst the processor continues to execute instructions during clock cycles of the processor. The instruction execution of the processor is monitored by counting the number of successive instructions which are retired contiguously in time to form an instruction count, and counting the number of subsequent contiguous clock cycles of the processor during which no instruction is retired to form a stall count. A trace message is generated which includes the instruction count and the stall count, and the trace message is outputted.
Claims17
A method of tracing instruction execution on a processor of an integrated circuit chip in real time whilst the processor continues to execute instructions during clock cycles of the processor, the method comprising:
- at tracing circuitry on the integrated circuit chip:
- monitoring the instruction execution of the processor by:
- counting, using an instruction counter, a number of successively retired instructions to form an instruction count, wherein the successively retired instructions are generated contiguously in time, wherein the instruction counter stops counting when the instruction counter identifies a time gap in which the processor does not retire an instruction;
- and
- counting, using a stall counter, a number of subsequent contiguous clock cycles of the processor during which no instruction is retired to form a stall count, wherein, in response to a signal from the instruction counter identifying that the instruction counter has stopped the counting, the stall counter starts counting immediately following an end of a series of successively retired instructions that are generated contiguously in time;
- generating a trace message which comprises the instruction count and the stall count;
- and
- outputting the trace message.
A method of tracing instruction execution on a processor of an integrated circuit chip in real time whilst the processor continues to execute multiple instructions contemporaneously during clock cycles of the processor, the processor being capable of retiring more than one instruction per clock cycle, the method comprising:
- at tracing circuitry on the integrated circuit chip:
- monitoring the instruction execution of the processor by:
- counting, using an instruction counter, a number of instructions successively retired in each clock cycle to form a clock cycle count, wherein the successively retired instructions are generated contiguously in time and wherein the instruction counter stops counting when the instruction counter identifies a time gap in which the processor does not retire an instruction;
- and
- counting, using a stall counter, a number of contiguous clock cycles of the processor during which no instruction is retired to form a stall count, wherein, in response to a signal from the instruction counter identifying that the instruction counter has stopped the counting, the stall counter starts counting immediately following an end of a series of successively retired instructions that are generated contiguously in time;
- generating a trace message which comprises the clock cycle count and the stall count;
- and
- outputting the trace message.
An integrated circuit chip comprising:
- a processor configured to execute instructions during clock cycles of the processor;
- tracing circuitry configured to trace instruction execution of the processor in real time, the tracing circuitry comprising:
- an instruction counter configured to count a number of successively retired instructions to form an instruction count, wherein the successively retired instructions are generated contiguously in time, and wherein the instruction counter is configured to stop counting when the instruction counter identifies a time gap in which the processor does not retire an instruction;
- a stall counter configured to count a number of subsequent contiguous clock cycles of the processor during which no instruction is retired to form a stall count, wherein, in response to a signal from the instruction counter identifying that the instruction counter has stopped the counting, the stall counter is configured to start counting immediately following an end of a series of successively retired instructions that are generated contiguously in time;
- a message generator configured to generate a trace message which comprises the instruction count and the stall count;
- and
- an output configured to output the trace message.
An integrated circuit chip comprising:
- a processor configured to retire more than one instruction per clock cycle of the processor;
- tracing circuitry configured to trace instruction execution of the processor in real time, the tracing circuitry comprising:
- a clock cycle counter configured to count a number of instructions successively retired in each clock cycle to form a clock cycle count, wherein the successively retired instructions are generated contiguously in time;
- a stall counter configured to count a number of contiguous clock cycles of the processor during which no instruction is retired to form a stall count, wherein, in response to a signal from the clock cycle counter identifying that the clock cycle counter has stopped the counting, the stall counter is configured to start counting immediately following an end of a series of successively retired instructions that are generated contiguously in time;
- a message generator configured to generate a trace message which comprises the clock cycle count and the stall count;
- and
- an output configured to output the trace message.
Dependencies are inferred from the claim text.