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US 11,907,066 B2Granted
Managing storage of multiple plane parity data in a memory sub-system
AssigneeMicron Technology, Inc.
InventorsXiangang Luo, Jianmin Huang, Lakshmi Kalpana Vakati, Harish R. Singidi
Life of this patent
Estimating the term…
Abstract
A parity generation operation based on a set of multiple planes of host data is executed to generate a set of multi-page parity data. The set of multi-page parity data is stored in a cache memory of a memory device. A data recovery operation is performed based on the set of multi-page parity data.
Claims17
A method comprising:
- executing a first parity generation operation based on a set of multiple planes of host data to generate a set of multi-page parity data associated with a memory device;
- storing the set of multi-page parity data in a cache memory of the memory device;
- executing a second parity generation operation based on multiple sub-blocks of the host data to generate multi-plane multi-sub-block parity data;
- and
- in response to a multi-plane failure, performing, by a processing device, a data recovery operation based on the set of multi-page parity data and the multi-plane multi-sub-block parity data associated with the host data.
2 more elements
A non-transitory computer readable medium comprising instructions, which when executed by a processing device, cause the processing device to perform operations comprising:
- executing a first parity generation operation based on a set of multiple planes of host data to generate a set of multi-page parity data associated with a memory device;
- storing the set of multi-page parity data in a cache memory of the memory device;
- executing a second parity generation operation based on multiple sub-blocks of the host data to generate multi-plane multi-sub-block parity data;
- and
- in response to a multi-plane failure, performing, by a processing device, a data recovery operation based on the set of multi-page parity data and the multi-plane multi-sub-block parity data associated with the host data.
2 more elements
A system comprising:
- a memory device;
- and
- a processing device, operatively coupled with the memory device, to perform operations comprising:
- executing a first parity generation operation based on a set of multiple planes of host data to generate a set of multi-page parity data associated with a memory device;
- storing the set of multi-page parity data in a cache memory of the memory device;
- executing a second parity generation operation based on multiple sub-blocks of the host data to generate multi-plane multi-sub-block parity data;
- and
- in response to a multi-plane failure, performing, by a processing device, a data recovery operation based on the set of multi-page parity data and of the multi-plane multi-sub-block parity data associated with the host data.
5 more elements
Dependencies are inferred from the claim text.