Adaptive wake-up for power conservation in a processor

An electronic device comprising:

• a first processor;
• and
• a second processor coupled to the first processor,
• wherein the second processor includes:
• a plurality of processing pipelines associated with different tasks, the plurality of processing pipelines including:
• a first pipeline having a first memory circuit and a first logic circuit configured to process a physical downlink control channel;
• a second pipeline having a second memory circuit and a second logic circuit configured to process a physical downlink shared channel;
• and
• a third pipeline having a third memory circuit and a third logic circuit configured to process one or more physical uplink channels;
• and
• a power management circuit configured to manage one or more power states, including:
• a sleep state in which the first, second, and third memory circuits and the first, second, and third logic circuits are in a low power state;
• a listening state in which the first memory circuit and the first logic circuit are powered up while the second and third memory circuits and the second and third logic circuits are in the low power state;
• and
• a data communication state in which the first, second, and third memory circuits and the first, second, and third logic circuits are powered up, wherein the power management circuit is further configured to:
• periodically transition from the sleep state to the listening state;
• while in the listening state, determine whether data communication should be enabled and transition from the listening state to the data communication state in response to determining that data communication should be enabled;
• and
• while in the data communication state, determine data communication has ended and transition from the data communication state to the sleep state in response to determining that data communication has ended.

A method implemented in a processor, the method comprising:

• placing the processor into a sleep state in which a plurality of processing pipelines are in a low power state, wherein the plurality of processing pipelines includes a first pipeline having a first memory circuit and a first logic circuit configured to process a physical downlink control channel, a second pipeline having a second memory circuit and a second logic circuit configured to process a physical downlink shared channel, and a third pipeline having a third memory circuit and a third logic circuit configured to process one or more physical uplink channels;
• determining when a paging interval has elapsed;
• in response to determining that the paging interval has elapsed:
• entering a listening state, wherein entering the listening state includes powering up the first pipeline including the first memory circuit and the first logic circuit;
• and
• determining, based at least in part on downlink control information received using the first pipeline, whether a base station has data ready to send to the processor;
• in response to determining that the base station has data ready to send, entering a data communication state, wherein entering the data communication state includes powering up the second and third memory circuits and the second and third logic circuits;
• determining that the data communication state should be exited;
• and
• in response to determining that the data communication state should be exited, returning to the sleep state, wherein returning to the sleep state includes powering down the first, second, and third memory circuits and the first, second, and third logic circuits.