Memory power management method and processor system

A processor system comprising a processor coupled to a memory comprising a plurality of memory banks, the memory further comprising a region configurable as a heap region, wherein the processor is operable to execute instructions comprising one or more cryptographic operations;

• and wherein the processor system is configured to:
• allocate at least one memory bank to the heap region dependent on a predetermined memory size required for execution of at least one cryptographic operation;
• allocate at least one further memory bank to the heap region;
• and
• further configured to switch from a first operating mode to a second operating mode by:
• setting the at least one memory bank to an active state;
• setting the at least one further memory bank to an active state;
• and
• to switch from the second operating mode to the first operating mode by:
• setting the at least one memory bank to a retention state;
• setting the at least one further memory bank to a power-down state.

A non-transitory computer readable media comprising a computer program comprising computer executable instructions which, when executed by a processor system including a processor coupled to a memory comprising a plurality of memory banks, causes the processor to perform the steps of

• allocating at least one memory bank to the heap region dependent on a predetermined memory size required for execution of at least one cryptographic operation;
• allocating at least one further memory bank to the heap region;
• and
• switching from a first operating mode to a second operating mode by:
• setting the at least one memory bank to an active state;
• setting the at least one further memory bank to an active state;
• and
• switching from the second operating mode to the first operating mode by:
• setting the at least one memory bank to a retention state;
• setting the at least one further memory bank to a power-down state.