Clock management circuit and multi-core system including the same

A multi-core system comprising:

• a multi-core processor including a first processor core configured to operate based on a first core clock signal and a second processor core configured to operate based on a second core clock signal;
• a function block configured to communicate with the multi-core processor based on an interface clock signal;
• and
• a clock management circuit configured to:
• generate the first core clock signal by selecting one of a first clock signal having a first frequency and a second clock signal having a second frequency different from the first frequency based on a first frequency selection signal,
• generate the second core clock signal by selecting one of the first clock signal and the second clock signal based on a second frequency selection signal,
• generate the interface clock signal based on the second clock signal, and
• when at least one of a frequency of the first core clock signal and a frequency of the second core clock signal is changed, simultaneously deactivate the first core clock signal, the second core clock signal and the interface clock signal in a clock gating period.

A clock management circuit comprising:

• a synchronization circuit configured to generate a clock gating signal that is activated to control a clock gating period when a frequency of at least one of a plurality of core clock signals provided to a plurality of processor cores of a multi-core system is changed;
• a plurality of clock switching circuits configured to a plurality of switching clock signals by selecting one of a first clock signal having a first frequency and a second clock signal having a second frequency different from the first frequency;
• a plurality of core clock gating circuits configured to generate the plurality of core clock signals respectively corresponding to the plurality of switching clock signals by deactivating the plurality of switching clock signals in the clock gating period based on the clock gating signal;
• and
• an interface clock gating circuit configured to generate an interface clock signal provided to a function block of the multi-core system by deactivating the second clock signal in the clock gating period based on the clock gating signal.