Low-dropout (LDO) voltage regulator including amplifier and decoupling capacitor
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsSzu-Chun Tsao, Yi-Wen Chen, Jaw-Juinn Horng
Life of this patent
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Abstract
A middle-range (mid) low dropout (LDO) voltage has both sinking and sourcing current capability. The mid LDO can provide a voltage reference in active mode and power mode for core only design to work in a Safe Operating Area (SOA). The output of mid LDO can track TO power and/or core power dynamically. The mid LDO can comprise a voltage reference generator and a power-down controller connected to an amplifier, which output is connected to a decoupling capacitor. The provision of a high ground signal allows the mid LDO provide the sinking and sourcing currents.
Claims20
A Low-Dropout voltage regulator (LDO) comprising:
- an amplifier supplied with a voltage reference (VREF) input, the amplifier configured to produce a source current to or a sinking current from a load;
- and
- a decoupling capacitor, connected to an output of the amplifier, configured to decouple a high-edge ground (HGND) from a power source, the decoupling capacitor including a first capacitor and a second capacitor attached with the load, wherein the first capacitor is a pure Metal-Oxide-Metal (MOM) capacitor (CMOM) and the second capacitor is a core P-type Metal Oxide Semiconductor Capacitor (PMOSCAP), wherein one or more Metal Oxide Semiconductor Field Effect Transistors (MOSFETS) is placed beneath the CMOM to get a highest capacitance density.
A level shifter comprising:
- a Low-Dropout voltage regulator (LDO) comprising:
- an amplifier configured to produce a source current to or a sinking current from a load;
- a Voltage Reference Generator (VREFGEN) circuit, connected to an input of the amplifier, configured to track a fixed voltage reference (VREF) and supply a voltage reference output (VREFM) to the amplifier;
- a decoupling capacitor, connected to an output of the amplifier, configured to decouple a high-edge ground (HGND) from a power source;
- and
- a Power Down Control Unit (PDCTRL) configured to maintain the HGND in an active mode or a power-down mode;
- wherein the VREFM of the LDO is directly forced by an input voltage or is forced through the VREFGEN, which is configured to transfer directly a difference between a core power and an IO power.
A method comprising:
- receiving a voltage reference input at a Low-Dropout voltage regulator (LDO);
- receiving an Input/Output (IO) power at the LDO;
- receiving a high-edge ground (HGND) from a power source;
- and
- providing an output voltage from the LDO to a core design, wherein the output voltage is a difference between the IO power and the HGND, wherein providing the output voltage comprises:
- in a first configuration, producing a source current to the core design;
- or
- in a second configuration, receiving a sinking current from the core design,
- tracking a second difference between the IO power and a core power to supply the voltage reference input to the LDO, wherein tracking the second difference comprises:
- transforming core power information into a current through a core diode-connected Metal-Oxide Semiconductor Field Effect Transistor (MOSFET) and a resistor in series;
- and
- generating the voltage reference input for the LIDO through a second diode-connected MOSFET and a second resistor between the IO power and the reference voltage input to the LDO.
Dependencies are inferred from the claim text.