Display device and semiconductor device

A display device comprising:

• a semiconductor layer including a first region, a second region and a channel region between the first region and the second region;
• a first insulating layer located on the semiconductor layer;
• a gate electrode located on the first insulating layer and opposing the channel region;
• a second insulating layer located on the first insulating layer and the gate electrode;
• a third insulating layer located on the second insulating layer;
• a fourth insulating layer located on the third insulating layer;
• an alignment film covering the fourth insulating layer;
• a plurality of transparent conductive layers located between the second insulating layer and the alignment film;
• a plurality of gate lines extending in a first direction and arranged in a second direction intersecting the first direction, with intervals therebetween;
• and
• a plurality of source lines extending in the second direction and arranged in the first direction with intervals therebetween, to intersect the plurality of gate lines,
• the plurality of transparent conductive layers including a pixel electrode between the fourth insulating layer and the alignment film, a first conductive layer between the second insulating layer and the third insulating layer, and a second conductive layer between the third insulating layer and the fourth insulating layer,
• the first conductive layer being in contact with the second region of the semiconductor layer through a first contact hole formed in the first insulating layer and the second insulating layer,
• the second conductive layer being in contact with the first conductive layer through a second contact hole formed in the third insulating layer,
• the pixel electrode being in contact with the second conductive layer through a third contact hole formed in the fourth insulating layer,
• the fourth insulating layer being in contact with the second conductive layer inside of the second contact hole,
• the gate electrode being electrically connected to one of the plurality of gate lines and being located in a region where a respective one of the plurality of gate lines and a respective one of the plurality of source lines overlap,
• the first region being electrically connected to one of the plurality of source lines,
• the first conductive layer being located in an open area surrounded by a respective adjacent pair of gate lines of the plurality of gate lines and a respective adjacent pair of source lines of the plurality of source lines,
• a width of the open area in the second direction is being less than a width of the gate line in the second direction.