MOS transistor isolated from the substrate of an integrated circuit and application for detecting an opening of a closed container

A method for detecting whether a severable part of an electrically conductive wire connecting first and second terminals of an integrated circuit has been severed in the event of an opening or attempted opening of a closed container, comprising:

• charging a first capacitor electrically isolated from a first substrate of the integrated circuit and connected to the first terminal;
• charging a second capacitor electrically isolated from the first substrate of the integrated circuit and having a first electrode connected to a drain region of a first MOS transistor;
• and
• using said first MOS transistor to take at least one measurement of a voltage of the first electrode of the second capacitor and compare the measured voltage to a threshold.

A system, comprising:

• an integrated circuit, including:
• a first substrate;
• and
• a first MOS transistor having a first polysilicon region electrically isolated from the first substrate and including a gate region, a second polysilicon region electrically isolated from the first polysilicon region and from the first substrate, said second polysilicon region including a source region, a substrate region and a drain region of said first MOS transistor, wherein the first polysilicon region is located between an area of the first substrate and the second polysilicon region;
• wherein the first MOS transistor is a PMOS transistor;
• and
• wherein the source region the first MOS transistor connected to ground and wherein the first MOS transistor has a threshold voltage such that it is in an on state in response to a zero voltage is applied to the gate region and in an off state in in response to a negative bias applied to the gate region.

A system, comprising:

• an integrated circuit, including:
• a first substrate;
• and
• a first MOS transistor having a first polysilicon region electrically isolated from the first substrate and including a gate region, a second polysilicon region electrically isolated from the first polysilicon region and from the first substrate, said second polysilicon region including a source region, a substrate region and a drain region of said first MOS transistor, wherein the first polysilicon region is located between an area of the first substrate and the second polysilicon region;
• wherein the integrated circuit further comprises:
• an isolation trench located in the first substrate;
• and
• a dielectric layer surrounding the first polysilicon region, wherein the first polysilicon region is surrounded by the dielectric layer thereof extending through the isolation trench into the first substrate, and wherein the substrate region of the first MOS transistor rests at least partially on one end of the first polysilicon region surrounded by said dielectric layer and the source and drain regions resting on the isolation trench.

A system, comprising:

• an integrated circuit, including:
• a first substrate;
• and
• a first MOS transistor having a first polysilicon region electrically isolated from the first substrate and including a gate region, a second polysilicon region electrically isolated from the first polysilicon region and from the first substrate, said second polysilicon region including a source region, a substrate region and a drain region of said first MOS transistor, wherein the first polysilicon region is located between an area of the first substrate and the second polysilicon region;
• wherein the integrated circuit further comprises:
• a dielectric layer disposed between the first polysilicon region and the first substrate;
• and
• a second MOS transistor including, in the first substrate, a source region, a drain region and a substrate region between the source and drain regions and covered by said dielectric layer, the first polysilicon region including a gate region common to the first MOS transistor and to the second MOS transistor.