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US 11,894,297 B2Granted
Metal-insulator-metal capacitor having electrodes with increasing thickness
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorI-Che Lee
Life of this patent
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Abstract
Disclosed are metal-insulator-metal capacitors and integrated chips. In one embodiment, a metal-insulator-metal capacitor includes N electrodes and (N−1) passivation layers, wherein the N electrodes and the (N−1) passivation layers are alternately stacked on a substrate. N is an integer larger than 1. Thicknesses of the N electrodes gradually increase in a direction parallel to a normal direction of the substrate.
Claims20
A metal-insulator-metal capacitor, comprising:
- N electrodes and (N−1) passivation layers, wherein the N electrodes and the (N−1) passivation layers are alternately stacked on a substrate, N is an integer larger than 2, the N electrodes comprise an mth electrode to an Nth electrode sequentially arranged in a direction parallel to a normal direction of the substrate, m is 1 to N−1, a thickness of the mth electrode is smaller than a thickness of the Nth electrode, the thickness of the mth electrode is less than or equal to a thickness of the m+1th electrode, and wherein:
- a first electrode among the N electrodes is disposed on the substrate,
- a first passivation layer among the (N−1) passivation layers is disposed on the first electrode and the substrate, and the first passivation layer has a step region that continuously contacts and extends from a top surface of the first electrode to sidewalls of the first electrode, and
- a second electrode among the N electrodes is disposed on the first passivation layer, and the second electrode has a step region that continuously contacts and extends from a top surface of the first passivation layer to sidewalls of the first passivation layer.
1 more element
An integrated chip, comprising:
- an interconnect structure overlying a substrate;
- and
- a metal-insulator-metal capacitor disposed on the interconnect structure and comprising:
- N electrodes and (N−1) passivation layers, wherein the N electrodes and the (N−1) passivation layers are alternately stacked on the interconnect structure, N is an integer larger than 2, the N electrodes comprise an mth electrode to an Nth electrode sequentially arranged in a direction parallel to a normal direction of the substrate, m is 1 to N−1, a thickness of the mth electrode is smaller than a thickness of the Nth electrode, the thickness of the mth electrode is less than or equal to a thickness of the m+1th electrode, and wherein:
- a first electrode among the N electrodes is disposed on the substrate,
- a first passivation layer among the (N−1) passivation layers is disposed on the first electrode and the substrate, and the first passivation layer has a step region that continuously contacts and extends from a top surface of the first electrode to sidewalls of the first electrode, and
- a second electrode among the N electrodes is disposed on the first passivation layer, and the second electrode has a step region that continuously contacts and extends from a top surface of the first passivation layer to sidewalls of the first passivation layer.
4 more elements
An integrated chip, comprising:
- an interconnect structure overlying a substrate;
- and
- a metal-insulator-metal capacitor disposed in the interconnect structure and comprising:
- N electrodes and (N−1) passivation layers, wherein the N electrodes and the (N−1) passivation layers are alternately stacked in the interconnect structure, N is an integer larger than 2, the N electrodes comprise an mth electrode to an Nth electrode sequentially arranged in a direction parallel to a normal direction of the substrate, m is 1 to N−1, a thickness of the mth electrode is smaller than a thickness of the Nth electrode, the thickness of the mth electrode is less than or equal to a thickness of the m+1th electrode, and wherein:
- a first electrode among the N electrodes is disposed on the substrate,
- a first passivation layer among the (N−1) passivation layers is disposed on the first electrode and the substrate, and the first passivation layer has a step region that continuously contacts and extends from a top surface of the first electrode to sidewalls of the first electrode, and
- a second electrode among the N electrodes is disposed on the first passivation layer, and the second electrode has a step region that continuously contacts and extends from a top surface of the first passivation layer to sidewalls of the first passivation layer.
4 more elements
Dependencies are inferred from the claim text.