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US 11,863,189 B2Granted
Input buffer circuit
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYu-Kai Tsai, Chia-Hui Chen, Chia-Jung Chang
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Abstract
An integrated circuit includes an upper threshold circuit, a lower threshold circuit, and a control circuit. The upper threshold circuit is configured to set a logic level of a first enabling signal based on comparing an input voltage signal with an upper threshold voltage. The lower threshold circuit is configured to set a logic level of a second enabling signal based on comparing the input voltage signal with a lower threshold voltage. The control circuit is configured to change an output voltage signal from a first voltage level to a second voltage level when the logic level of the first enabling signal and the logic level of the second enabling signal are changed consecutively.
Claims20
An integrated circuit comprising:
- an upper threshold circuit electrically connected to a first power domain and configured to set a logic level of a first enabling signal based on comparing an input voltage signal with an upper threshold voltage, wherein the upper threshold circuit includes a first tracker configured to receive the input voltage signal and an upper threshold detector configured to generate the first enabling signal in response to a first signal received from the first tracker;
- a first switch electrically connected between an upper supply voltage and a buffer output node, wherein the first switch is configured to be controlled by the first enabling signal;
- a lower threshold circuit electrically connected to a second power domain and configured to set a logic level of a second enabling signal based on comparing the input voltage signal with a lower threshold voltage, wherein the lower threshold circuit includes a second tracker configured to receive the input voltage signal and a lower threshold detector configured to generate the second enabling signal in response to a second signal received from the second tracker;
- a second switch electrically connected between the buffer output node and a lower supply voltage wherein the second switch is configured to be controlled by the second enabling signal;
- and
- a control circuit configured to change an output voltage signal from a first voltage level to a second voltage level when the logic level of the first enabling signal and the logic level of the second enabling signal are changed consecutively, the control circuit comprising a regenerative circuit having at least one switch, and wherein a connection state of the at least one switch between the buffer output node and one of the upper supply voltage or the lower supply voltage is configured to be controlled with a voltage on the buffer output node.
3 more elements
A method comprising:
- generating a first enabling signal based on comparing an input voltage signal with an upper threshold voltage, wherein generating the first enabling signal includes generating the first enabling signal with an upper threshold circuit in response to a first signal received from a first tracker coupled to the input voltage signal;
- controlling a first switch with the first enabling signal, wherein the first switch is electrically connected between an upper supply voltage and a buffer output node;
- generating a second enabling signal based on comparing the input voltage signal with a lower threshold voltage, wherein generating the second enabling signal includes generating the second enabling signal with a lower threshold circuit in response to a second signal received from a second tracker coupled to the input voltage signal;
- controlling a second switch with the second enabling signal, wherein the second switch is electrically connected between the buffer output node and a lower supply voltage;
- controlling at least one switch in a regenerative circuit with a voltage on the buffer output node to change a connection state of the at least one switch between the buffer output node and one of the upper supply voltage or the lower supply voltage;
- and
- changing an output voltage signal from a first voltage level to a second voltage level when each of the first enabling signal and the second enabling signal changes a logical level consecutively.
4 more elements
An integrated circuit comprising:
- an upper threshold circuit electrically connected to a first power domain and configured to set a logic level of a first enabling signal based on comparing an input voltage signal with an upper threshold voltage, wherein the upper threshold circuit includes a first tracker configured to receive the input voltage signal and an upper threshold detector configured to generate the first enabling signal in response to a first signal received from the first tracker;
- a lower threshold circuit electrically connected to a second power domain and configured to set a logic level of a second enabling signal based on comparing the input voltage signal with a lower threshold voltage, wherein the lower threshold circuit includes a second tracker configured to receive the input voltage signal and a lower threshold detector configured to generate the second enabling signal in response to a second signal received from the second tracker;
- a first switch electrically connected between an upper supply voltage and a buffer output node and configured to receive the first enabling signal from the upper threshold circuit;
- a second switch electrically connected between the buffer output node and a lower supply voltage and configured to receive the second enabling signal from the lower threshold circuit;
- and
- a regenerative circuit having at least one switch coupled between the buffer output node and one of the upper supply voltage or the lower supply voltage, and wherein a connection state of the at least one switch between the buffer output node and one of the upper supply voltage or the lower supply voltage is configured to be controlled with a voltage on the buffer output node.
3 more elements
Dependencies are inferred from the claim text.