US 11,855,630 B2Granted

Floating high-voltage level translator with adaptive bypass circuit

AssigneeTexas Instruments Incorporated

InventorsTuli Luthuli Dake, Satish Kumar Vemuri

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Abstract

Techniques are described herein to enhance capability of floating level translators. For example, increased headroom is accomplished by adaptively bypassing the protection elements of the voltage level translator. In an example, a floating level translator can translate an input signal from a low-voltage domain to a high-voltage domain. A bypass circuit is coupled across the protection elements. The bypass circuit selectively engages during low-voltage operation (e.g., thereby providing a lower loss path relative to loss caused by the high-voltage protection elements and thus increasing the headroom swing), and disengages responsive to the high-voltage reference rail of the high-voltage domain exceeding a threshold or otherwise being high enough (e.g., greater than the potential of the low-voltage domain power rail). The bypass circuit can be implemented in a relatively low-complexity manner (e.g., back-to-back high-voltage FETs) without additional signals to control low-voltage capability.

Claims12

Dependent claims

A voltage level translator circuit, comprising:

a first field effect transistor (FET) having first and second current terminals and a first control terminal, wherein the first current terminal is coupled to a first supply reference terminal, and the first control terminal is configurable to receive an input signal;
a second FET having third and fourth current terminals and a second control terminal, wherein the third current terminal is coupled to the first supply reference terminal, and the second control terminal is configurable to receive an inverted version of the input signal;
a third FET having fifth and sixth current terminals and a third control terminal, wherein the fifth current terminal is coupled to the second current terminal, the third control terminal is coupled to a floating second supply reference terminal, and the sixth current terminal is coupled to a first output terminal;
a fourth FET having seventh and eighth current terminals and a fourth control terminal, wherein the seventh current terminal is coupled to the fourth current terminal, the fourth control terminal is coupled to the floating second supply reference terminal, and the eighth current terminal is coupled to a second output terminal;
a fifth FET having ninth and tenth current terminals and a fifth control terminal, wherein the ninth current terminal is coupled to a floating supply power terminal, the tenth current terminal is coupled to the first output terminal, and the fifth control terminal is coupled to the second output terminal;
a sixth FET having eleventh and twelfth current terminals and a sixth control terminal, wherein the eleventh current terminal is coupled to the floating supply power terminal, the twelfth current terminal is coupled to the second output terminal, and the fifth control terminal is coupled to the first output terminal;
a first bypass circuit coupled between the first output terminal and the third control terminal, wherein the first bypass circuit includes:
a seventh FET coupled between the first output terminal and a first connection terminal, and having a seventh control terminal coupled to the first control terminal;
and
an eighth FET coupled between the first connection terminal and the third control terminal, and having an eighth control terminal coupled to the seventh control terminal;
and
a second bypass circuit coupled between the second output terminal and the fourth control terminal, wherein the second bypass circuit includes:
a ninth FET coupled between the second output terminal and a second connection terminal, and having a ninth control terminal coupled to the second control terminal;
and
a tenth FET coupled between the second connection terminal and the fourth control terminal, and having a tenth control terminal coupled to the eighth control terminal.

12 more elements

A voltage level translator circuit, comprising:

a first n-type field effect transistor (NFET) and a second NFET, each having a respective source coupled to a ground terminal, wherein a gate of the first NFET is configured to receive a pulse width modulated (PWM) input signal, and a gate of the second NFET is configured to receive an inverted version of the PWM input signal;
a first p-type field effect transistor (PFET) and a second PFET, each having a respective gate coupled to a floating supply reference terminal, wherein a drain of the first PFET is coupled to a drain of the first NFET, a drain of the second PFET is coupled to a drain of the second NFET, a source of the first PFET is coupled to a first output terminal, and a source of the second PFET is coupled to a second output terminal;
a third PFET and a fourth PFET, each having a respective source coupled to a floating first supply power terminal, a drain of the third PFET is coupled to the first output terminal, a drain of the fourth PFET is coupled to the second output terminal, a gate of the third PFET is coupled to the second output terminal, and a gate of the fourth PFET is coupled to the first output terminal;
a first bypass circuit that includes a third NFET and a fourth NFET, wherein a drain of the third NFET is coupled to the first output terminal, a source of the third NFET is coupled to a source of the fourth NFET, a drain of the fourth NFET is coupled to the gate of the first PFET, and respective gates of the third and fourth NFETs are configurable to receive the PWM input signal;
a second bypass circuit that includes a fifth NFET and a sixth NFET, wherein a drain of the fifth NFET is coupled to the second output terminal, a source of the fifth NFET is coupled to a source of the sixth NFET, a drain of the sixth NFET is coupled to the gate of the second PFET, and respective gates of the fifth and sixth NFETs are configured to receive the inverted version of the PWM input signal;
and
an inverter configurable to provide the inverted version of the PWM input signal, wherein the inverter is coupled to a second supply power terminal.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/828,797Filed 31 May 2022
Published: US 2023/0387916 A130 Nov 2023
Granted: 26 Dec 2023
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H03K 3/356182
Using complementary field-effect transistors: with additional means for controlling the main nodes
H03K 19/018528
Of complementary type, e.g. CMOS: with at least one differential stage
G01R 19/16566
Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values: circuits…
H03K 3/356113
Using complementary field-effect transistors: using additional transistors in the input circuit