Startup protection for standby amplifiers
AssigneeMicron Technology, Inc.
InventorsMishal Kumar, Wei Lu Chu
Life of this patent
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Abstract
Embodiments herein relate to protection of a standby amplifier of a memory device. Specifically, an input voltage of the standby amplifier may be reduced to decrease an occurrence of damage to the standby amplifier or components thereof. In some embodiments, the input voltage may be reduced using a voltage divider that provides the reduced input voltage to the standby amplifier during a power up operation. Upon completion of the power up operation, the input voltage of the standby amplifier may return to an operating voltage. The reduced input voltage may reduce the occurrence of damage to the standby amplifier by maintaining a gate to drain voltage of one or more transistors of the standby amplifier below a maximum.
Claims20
A standby amplifier comprising:
- an operational transconductance amplifier comprising a first input pair of transistors and a second input pair of transistors;
- a protection circuit comprising a first protection transistor coupled to the first input pair of transistors and a second protection transistor coupled to second input pair of transistors, the first protection transistor configured to selectively couple the first input pair of transistors to a voltage level based on an enable voltage, the second protection transistor configured to selectively couple the second input pair of transistors to a voltage level based on a reduced enable voltage;
- and
- an enable circuit for generating the reduced enable voltage comprising a voltage divider to reduce an enable voltage to be less than a maximum drain voltage of a first transistor of the first input pair of transistors.
A memory device comprising:
- a memory array comprising a plurality of memory cells arranged in a plurality of memory cell rows and a plurality of memory cell columns, wherein each memory cell of the plurality of memory cells is configured to store a data bit;
- a standby amplifier coupled to the memory array comprising a first input pair of transistors and a second input pair of transistors;
- a protection circuit comprising a first protection transistor coupled to the first input pair of transistors and a second protection transistor coupled to second input pair of transistors, the first protection transistor configured to selectively couple the first input pair of transistors to a voltage level based on an enable voltage, the second protection transistor configured to selectively couple the second input pair of transistors to a voltage level based on a reduced enable voltage;
- and
- an enable circuit for generating the reduced enable voltage comprising a voltage divider to reduce an enable voltage to be less than a maximum drain voltage of a first transistor of the first input pair of transistors.
A memory system comprising:
- a memory array comprising a plurality of memory cells arranged in a plurality of memory cell rows and a plurality of memory cell columns, wherein each memory cell of the plurality of memory cells is configured to store a data bit;
- a standby amplifier coupled to the memory array comprising a first input pair of transistors and a second input pair of transistors;
- an enable circuit for generating an enable voltage for the standby amplifier;
- a protection circuit comprising a first protection transistor coupled to the first input pair of transistors and a second protection transistor coupled to second input pair of transistors, the first protection transistor configured to selectively couple the first input pair of transistors to a voltage level based on the enable voltage, the second protection transistor configured to selectively couple the second input pair of transistors to a voltage level based on the enable voltage;
- and
- a reduced enable circuit to generate a reduced enable voltage based on the enable voltage, wherein the reduced enable voltage is less than the enable voltage.
Dependencies are inferred from the claim text.