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US 11,775,779 B2Granted
Hybrid analog-digital matrix processors
AssigneeLightmatter, Inc.
InventorsTyler J. Kenney, Martin B. Z. Forsythe, Tomo Lazovich, Darius Bunandar
Life of this patent
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Abstract
Techniques for computing matrix operations for arbitrarily large matrices on a finite-sized hybrid analog-digital matrix processor are described. Techniques for gain adjustment in a finite-sized hybrid analog-digital matrix processor are described which enable the system to obtain higher energy efficiencies, greater physical density and improved numerical accuracy. In some embodiments, these techniques enable maximization of the predictive accuracy of a GEMM-based convolutional neural network using low-precision data representations.
Claims29
An accelerator comprising:
- a plurality of digital-to-analog converters (DACs) configured to generate a plurality of input analog signals based on a data vector;
- an analog processor arranged to perform matrix-vector multiplication and comprising inputs and outputs;
- a plurality of n-bit analog-to-digital converters (ADCs) coupled to respective outputs of the analog processor, where n is equal to or less than 16;
- a plurality of analog amplifiers, coupled between the plurality of DACs and respective inputs of the analog processor, configured to generate a plurality of amplified input analog signals based on the plurality of input analog signals;
- and
- a controller configured to:
- receive a set of parameters representing a matrix;
- set a first gain of a first analog amplifier of the plurality of analog amplifiers and a second gain of a second amplifier of the plurality of analog amplifiers, wherein the first gain is different from the second gain;
- control the analog processor to generate a plurality of output analog signals based on the plurality of amplified input analog signals and the set of parameters;
- and
- control the plurality of ADCs to digitize the plurality of output analog signals.
8 more elements
A method for performing matrix-vector multiplication, comprising:
- generating a plurality of input analog signals based on a data vector;
- setting a first gain of a first multiplication unit of a plurality of multiplication units and a second gain of a second multiplication unit of the plurality of multiplication units, wherein the first gain is different from the second gain;
- controlling an analog processor based on a set of parameters representing a matrix;
- with the plurality of multiplication units, generating a plurality of scaled input analog signals by scaling the plurality of input analog signals;
- with the analog processor, generating a plurality of output analog signals based on the plurality of scaled input analog signals and the set of parameters;
- and
- controlling a plurality of n-bit analog-to-digital converters (ADCs), where n is equal to or less than 16, to digitize the plurality of output analog signals.
4 more elements
An accelerator comprising:
- a plurality of digital-to-analog converters (DACs) configured to generate a plurality of input analog signals based on a data vector;
- an analog processor arranged to generate a plurality of output analog signals by performing matrix-vector multiplication based on the plurality of input analog signals, the analog processor comprising inputs and outputs;
- a plurality of n-bit analog-to-digital converters (ADCs), where n is equal to or less than 16;
- a plurality of analog scaling units, coupled between respective outputs of the analog processor and the plurality of ADCs, configured to generate a plurality of scaled output analog signals based on the plurality of output analog signals;
- and
- a controller configured to:
- receive a set of parameters representing a matrix;
- set a first gain of a first analog scaling unit of the plurality of analog scaling units and a second gain of a second analog scaling unit of the plurality of analog scaling units, wherein the first gain is different from the second gain;
- and
- control the analog processor based on the set of parameters.
7 more elements
A method for performing matrix-vector multiplication, comprising:
- generating a plurality of input analog signals based on a data vector;
- setting a first gain of a first multiplication unit-of a plurality of multiplication units and a second gain of a second multiplication unit of the plurality of multiplication units, wherein the first gain is different from the second gain;
- controlling an analog processor based on a set of parameters representing a matrix;
- with the analog processor, generating a plurality of output analog signals based on the plurality of input analog signals and the set of parameters;
- with the plurality of multiplication units, generating a plurality of scaled output analog signals by scaling the plurality of output analog signals;
- and
- controlling a plurality of n-bit analog-to-digital converters (ADCs), where n is equal to or less than 16, to digitize the plurality of scaled output analog signals.
4 more elements
Dependencies are inferred from the claim text.