Back to results
US 11,757,434 B2Granted
High performance fast Mux-D scan flip-flop
AssigneeIntel Corporation
InventorsAmit Agarwal, Steven Hsu, Simeon Realov, Mahesh Kumashikar, Ram Krishnamurthy
Life of this patent
Estimating the term…
Abstract
A fast Mux-D scan flip-flop is provided, which bypasses a scan multiplexer to a master keeper side path, removing delay overhead of a traditional Mux-D scan topology. The design is compatible with simple scan methodology of Mux-D scan, while preserving smaller area and small number of inputs/outputs. Since scan Mux is not in the forward critical path, circuit topology has similar high performance as level-sensitive scan flip-flop and can be easily converted into bare pass-gate version. The new fast Mux-D scan flip-flop combines the advantages of the conventional LSSD and Mux-D scan flip-flop, without the disadvantages of each.
Claims17
An apparatus comprising:
- a latch that includes a data path and a scan path, wherein the latch includes:
- a transmission gate coupled on the data path between a data input and a keeper node;
- and
- a memory circuitry coupled to the keeper node, wherein the scan path is coupled to the memory circuitry, wherein the memory circuitry includes:
- a first tri-statable inverter having an input coupled to the keeper node;
- and
- a second tri-statable inverter having an input coupled to an output of the first tri-statable inverter and the scan path, wherein an output of the second tri-statable inverter is coupled to the keeper node;
- and
- scan clock circuitry to generate scan clock signals for a scan mode of the latch, the scan clock circuitry comprising:
- an inverter having an input and an output, wherein an input of the inverter is to receive an input clock;
- an AND logic coupled to the output of the inverter, wherein the AND logic is to receive a scan select signal;
- and
- an OR logic coupled to the input of the inverter, wherein the OR logic is to receive the scan select signal.
10 more elements
An apparatus comprising:
- a primary latch that includes:
- a data path and a scan path;
- a transmission gate coupled on the data path between a data input and a keeper node;
- a memory circuitry coupled to the keeper node, wherein the scan path is coupled to the memory circuitry;
- and
- a tri-statable inverter on the scan path with an input coupled to a scan input and an output coupled to the memory circuitry;
- a first inverter with an input coupled to the keeper node;
- a secondary latch with an input coupled to an output of the inverter;
- and
- scan clock circuitry to generate scan clock signals to control the transmission gate, the memory circuitry, and the tri-statable inverter for a scan mode of the apparatus, wherein the scan clock circuitry includes:
- a second inverter having an input and an output, wherein an input of the second inverter is to receive an input clock;
- an AND logic coupled to the output of the second inverter, wherein the AND logic is to receive a scan select signal;
- and
- an OR logic coupled to the input of the second inverter, wherein the OR logic is to receive the scan select signal.
11 more elements
A system comprising:
- a wireless communication interface;
- a memory;
- and
- a processor coupled to the memory and the wireless communication interface, the processor having a flip-flop that includes:
- a primary latch that includes a data path and a scan path, wherein the primary latch includes:
- a transmission gate coupled on the data path between a data input and a keeper node;
- and
- a memory circuitry coupled to the keeper node, wherein the scan path is coupled to the memory circuitry, wherein the memory circuitry includes:
- a first tri-statable inverter having an input coupled to the keeper node;
- and
- a second tri-statable inverter having an input coupled to an output of the first tri-statable inverter and the scan path, wherein an output of the second tri-statable inverter is coupled to the keeper node;
- a secondary latch coupled to an output of the primary latch;
- and
- scan clock circuitry to generate scan clock signals to control the primary latch, wherein the scan clock circuitry includes:
- an inverter having an input and an output, wherein an input of the inverter is to receive an input clock;
- an AND logic coupled to the output of the inverter, wherein the AND logic is to receive a scan select signal;
- and
- an OR logic coupled to the input of the inverter, wherein the OR logic is to receive the scan select signal.
15 more elements
Dependencies are inferred from the claim text.