Variable clock divider

An apparatus, comprising:

• a test circuit configured to generate signals for a test of a memory cell array in synchronization with a divided clock signal;
• and
• a clock divider circuit configured to generate the divided clock signal in response to a division ratio, the clock divider circuit comprising:
• a plurality of first latch circuits coupled in series;
• and
• a plurality of second latch circuits coupled in series, wherein
• each of the first latch circuits is configured to perform a latch operation in synchronization with one of a rise trigger signal and a fall trigger signal, the rise and fall trigger signals being alternately activated every odd clock cycles or every even clock cycles,
• each of the second latch circuits is configured to perform a latch operation in synchronization with another of the rise trigger signal and the fall trigger signal, and
• in response to the division ratio, one or more of the first latch circuits and one or more of the second latch circuits are bypassed, and remaining of the first and second latch circuits are cyclically coupled.

A semiconductor device, comprising:

• a memory cell array;
• an access control circuit configured to access the memory cell array by using an internal address signal and an internal command signal;
• and
• a test circuit configured to supply the internal address signal and the internal command signal to the access control circuit in synchronization with a first clock signal, the test circuit comprising:
• an oscillator circuit configured to generate an oscillator signal;
• a clock divider circuit configured to generate a divided clock signal by using a plurality of latch circuits coupled cyclically;
• and
• a multiplexer configured to supply the first clock signal as one of the oscillator signal and the divided clock signal based on a clock selection signal, wherein
• the plurality of latch circuits include a first group of latch circuits and a second group of latch circuits,
• an output signal of one latch circuit of the first group is a rise trigger signal and an output signal of one latch circuit of the second group is a fall trigger signal,
• when the fall trigger signal is activated, the rise trigger signal is generated by passage of a one-shot pulse through the one latch circuit of the first group and at least one latch circuit of the second group and, and
• when the rise trigger signal is activated, the fall trigger signal is generated by passage of a one-shot pulse through the one latch circuit of the second group and at least one latch circuit of the first group.