Clock crossing FIFO status converged synchronizer
AssigneeIntel Corporation
InventorsLeon Zlotnik, Jeremy Anderson, Lev Zlotnik, Daniel Ballegeer
Life of this patent
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Abstract
A synchronizer that can generate pipeline (e.g., FIFO, LIFO) status in a single step without intermediate synchronization. The status can be an indicator of whether a pipeline is full, empty, almost full, or almost empty. The synchronizer (also referred to as a double-sync or ripple-based pipeline status synchronizer) can be used with any kind of clock crossing pipeline and all kinds of pointer encodings. The double-sync and ripple-based pipeline status synchronizers eliminate costly validation and semi-manual timing closure, suggests better performance and testability, and have lower area and power.
Claims20
An apparatus comprising:
- a pipeline;
- a first set of pointers associated with the pipeline, wherein the first set of pointers are associated with a read clock used to read from the pipeline;
- a second set of pointers associated with the pipeline, wherein the second set of pointers are associated with a write clock used to write to the pipeline;
- comparators to compare the first set of pointers with the second set of pointers;
- a logic coupled to outputs of the comparators, wherein the logic is to perform an AND operation;
- a filter coupled to an output of the logic;
- a Schmitt trigger coupled to the filter;
- and
- at least two flip-flops coupled to the Schmitt trigger, wherein an output of one of the at least two flip-flops indicate a status of the pipeline.
An apparatus comprising:
- a pipeline;
- comparators to compare a first set of pointers with a second set of pointers, wherein the first set of pointers are associated with the pipeline to read from the pipeline, wherein the second set of pointers are associated with the pipeline to write to the pipeline;
- a logic coupled to outputs of the comparators, wherein the logic is to perform an AND operation on the outputs;
- and
- a pipeline status synchronizer coupled to the logic, wherein the pipeline status synchronizer is to provide an indicator of whether the pipeline is full, empty, almost full, or almost empty.
A system comprising:
- a memory;
- a processor coupled to the memory;
- and
- a wireless interface to allow the processor to communicate with another device, wherein the processor includes:
- a first-in-first-out (FIFO);
- a first set of pointers associated with the FIFO, wherein the first set of pointers are associated with a read clock used to read from the FIFO;
- a second set of pointers associated with the FIFO, wherein the second set of pointers are associated with a write clock used to write to the FIFO;
- comparators to compare the first set of pointers with the second set of pointers;
- a logic coupled to outputs of the comparators, wherein the logic is to perform an AND operation;
- a filter coupled to an output of the logic;
- a Schmitt trigger coupled to the filter;
- and
- two flip-flops coupled to the Schmitt trigger, wherein an output of one of the two flip-flops indicates a status of the FIFO.
Dependencies are inferred from the claim text.