High resistivity semiconductor-on-insulator wafer and a method of manufacture

A multilayer structure comprising:

• a single crystal semiconductor handle substrate comprising two major, generally parallel surfaces, one of which is a front surface of the single crystal semiconductor handle substrate and the other of which is a back surface of the single crystal semiconductor handle substrate, a circumferential edge joining the front and back surfaces of the single crystal semiconductor handle substrate, a central plane between the front surface and the back surface of the single crystal semiconductor handle substrate, and a bulk region between the front and back surfaces of the single crystal semiconductor handle substrate, wherein the single crystal semiconductor handle substrate has a minimum bulk region resistivity of at least about 500 ohm-cm;
• a semiconductor layer comprising amorphous silicon germanium having grain sizes of less than about 10 nanometers or polycrystalline silicon germanium having grain sizes of about 20 nanometers, wherein the amorphous silicon germanium or the polycrystalline silicon germanium has a molar percent of germanium of at least about 5 molar %, and further wherein the semiconductor layer comprises dislocations selected from the group consisting of misfit dislocations, threading dislocations, and a combination thereof, wherein a concentration of dislocations is between 1×105/cm2 and 1×1010/cm2;
• a dielectric layer comprising a material selected from the group consisting of silicon dioxide, silicon nitride, hafnium oxide, titanium oxide, zirconium oxide, lanthanum oxide, barium oxide, and a combination thereof;
• and
• a single crystal semiconductor device layer.