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US 11,688,739 B2Granted
Logic circuit capable of preventing latch-up
AssigneePixart Imaging Inc.
InventorsYung-Ju Wen, Han-Chi Liu, Hsin-You Ko
Life of this patent
Estimating the term…
Abstract
There is provided a logic circuit capable of preventing latch-up. The conducting of a parasitic SCR is prevented by doping an additional N+ active region in the N well region of a PMOS transistor and doping an additional P+ active region in the P well region of an NMOS transistor so as to prevent the occurrence of latch-up.
Claims11
A logic circuit, comprising:
- a PMOS transistor, comprising:
- an n-well region;
- a P+ active region, configured as a source of the PMOS transistor and arranged in the n-well region;
- an N+ active region, arranged in the n-well region and not configured as a guard ring;
- an N+ guard ring arranged in the n-well region to be physically separated from the N+ active region of the PMOS transistor;
- and
- a first contact, electrically in contact with the P+ active region and the N+ active region in the n-well region;
- an NMOS transistor, comprising:
- a p-well region;
- an N+ active region, configured as a source of the NMOS transistor and arranged in the p-well region;
- a P+ active region, arranged in the p-well region and not configured as a guard ring;
- and
- a second contact, electrically in contact with the N+ active region and the P+ active region in the p-well region;
- and
- an additional n-well region arranged between the PMOS transistor and the NMOS transistor, parallel to the N+ guard ring, and physically separated from the N+ guard ring of the PMOS transistor.
12 more elements
A logic circuit, comprising:
- a PMOS transistor and an NMOS transistor, wherein
- a gate of the PMOS transistor is electrically connected to a gate of the NMOS transistor via a poly routing extending along a first direction,
- a first contact of the PMOS transistor covers on a P+ active region, which is configured as a source of the PMOS transistor, and an additional N+ active region, which is not configured as a guard ring, adjacent to each other in the first direction in an n-well region, and
- a second contact of the NMOS transistor covers on an N+ active region, which is configured as a source of the NMOS transistor, and an additional P+ active region, which is not configured as a guard ring, adjacent to each other in the first direction in a p-well region;
- a third contact, covering on an N+ guard ring of the PMOS transistor, wherein
- the third contact and the first contact are physically separated on a surface of the PMOS transistor, and
- the N+ guard ring is physically separated from the additional N+ active region;
- and
- an additional n-well region arranged between the PMOS transistor and the NMOS transistor, parallel to the N+ guard ring, and physically separated from the N+ guard ring of the PMOS transistor.
6 more elements
Dependencies are inferred from the claim text.