Short circuit protection structure in MOS-gated power devices

A single chip power semiconductor device, comprising:

• a first load terminal;
• a second load terminal;
• a semiconductor body integrated in the single chip and coupled to the first load terminal and the second load terminal and configured to conduct a load current along a load current path between the first and second load terminals;
• a control terminal and at least one control electrode electrically connected to the control terminal, the at least one control electrode being electrically insulated from the semiconductor body and configured to control the load current based on a control voltage between the control terminal and the first load terminal;
• a protection structure integrated, separately from the load current path, in the single chip and comprising a series connection of a plurality of pn-junctions with a plurality of first semiconductor regions of a first conductivity type and a plurality of second semiconductor regions of a second conductivity type, the series connection of the pn-junctions being connected in forward bias between the control terminal and the first load terminal;
• an active cell region with one or more power cells integrated in the semiconductor body and configured for conduction of the load current;
• and
• an edge termination region surrounding the active cell region and terminated by a chip edge,
• wherein the first load terminal comprises a source pad structure laterally overlapping with the active region,
• wherein the control terminal comprises a control pad structure,
• wherein both the source pad structure and the control pad structure are arranged above a frontside of the semiconductor body,
• wherein at least an upper insulation layer of the single chip separates, along a vertical direction, both the source pad structure and the control pad structure from the frontside of the semiconductor body.

A single chip power semiconductor device, comprising:

• a first load terminal;
• a second load terminal;
• a semiconductor body integrated in the single chip and coupled to the first load terminal and the second load terminal and configured to conduct a load current along a load current path between the first and second load terminals;
• a control terminal and at least one control electrode electrically connected to the control terminal, the at least one control electrode being electrically insulated from the semiconductor body and configured to control the load current based on a control voltage between the control terminal and the first load terminal;
• a protection structure integrated, separately from the load current path, in the single chip and comprising a series connection of a plurality of pn-junctions with a plurality of first semiconductor regions of a first conductivity type and a plurality of second semiconductor regions of a second conductivity type, the series connection of the pn-junctions being connected in forward bias between the control terminal and the first load terminal,
• wherein the protection structure comprises a plurality of short circuit elements short circuiting np-junctions formed by pairs of a respective first semiconductor region and an adjacent second semiconductor region.