Adjustable delay line devices and methods thereof
AssigneeIntrinsix Corporation
InventorsKathiravan Krishnamurthi, Finbarr McGrath
Life of this patent
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Abstract
A switched delay section for an integrated circuit device is disclosed. The switched delay section includes a segmented inductor loop comprising a plurality of segments separated by nodes. A plurality of capacitors are coupled between the segmented inductor loop to provide a plurality of delay sections. An image loop is in electrical communication with the segmented inductor loop. The image loop includes a switch configured to place the plurality of capacitors in one of a high capacitance or a low capacitance state to provide a variable delay value.
Claims29
A switched delay section for an integrated circuit device comprising:
- a segmented inductor loop comprising a plurality of segments separated by nodes;
- a plurality of capacitors coupled between the segmented inductor loop to provide a plurality of delay sections;
- and
- a separate image loop in electrical communication with but not physically connected to the segmented inductor loop, the image loop comprising a switch in series with the image loop and configured to switch the plurality of segments between low and high inductance values by varying a mutual magnetic coupling between the segmented inductor loop and the image loop, wherein the plurality of capacitors are configured to be placed in one of a high capacitance or a low capacitance state to provide a variable delay value.
A method of making a switched delay section for an integrated circuit device comprising:
- providing a segmented inductor loop comprising a plurality of segments separated by nodes;
- locating a plurality of capacitors inside the segmented inductor loop to provide a plurality of delay sections;
- and
- providing a separate image loop in electrical communication with but not physically connected to the segmented inductor loop, the image loop comprising a switch in series with the image loop and configured to switch the plurality of segments between low and high inductance values by varying a mutual magnetic coupling between the segmented inductor loop and the image loop.
A cascaded switched delay section for an integrated circuit device comprising:
- a plurality of switched delay sections arranged in a cascaded configuration, each of the plurality of switched delay sections comprising:
- a segmented inductor loop comprising a plurality of segments separated by nodes;
- a plurality of capacitors located inside another segmented inductor loop to provide another plurality of delay sections;
- and
- a separate image loop in electrical communication with but not physically connected to the segmented inductor loop, the image loop comprising a switch in series with the image loop and and configured to switch the plurality of segments between low and high inductance values by varying a mutual magnetic coupling between the segmented inductor loop and the image loop.
A method of providing a variable delay for an integrated circuit device, the method comprising:
- providing a segmented inductor loop comprising a plurality of segments separated by nodes;
- locating a plurality of capacitors inside the segmented inductor loop to provide a plurality of delay sections;
- providing a separate image loop in electrical communication with but not physically connected to the segmented inductor loop, the image loop comprising a switch in series with the image loop and configured to switch the plurality of segments between low and high inductance values by varying a mutual magnetic coupling between the segmented inductor loop and the image loop;
- and
- operating the switch to provide a variable delay for the plurality of delay sections.
Dependencies are inferred from the claim text.