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US 11,641,747 B2Granted
Integration of a ferroelectric memory device with a transistor
AssigneeKepler Computing Inc.
InventorsGaurav Thareja, Sasikanth Manipatruni, Rajeev Kumar Dokania, Ramamoorthy Ramesh, Amrita Mathuriya
Life of this patent
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Abstract
Approaches for integrating FE memory arrays into a processor, and the resulting structures are described. Simultaneous integrations of regions with ferroelectric (FE) cells and regions with standard interconnects are also described. FE cells include FE capacitors that include a FE stack of layers, which is encapsulated with a protection material. The protection material protects the FE stack of layers as structures for regular logic are fabricated in the same die.
Claims19
An apparatus comprising:
- a transistor, comprising:
- a source;
- a drain;
- a gate electrode between the source and the drain;
- a drain contact coupled with the drain;
- a source contact coupled with the source;
- a gate contact coupled with the gate electrode;
- and
- a first via coupled with the drain contact, wherein the apparatus further comprises:
- a structure coupled to the first via, the structure comprising:
- a first etch stop layer (ESL) with a first discontinuity;
- an interlayer dielectric (ILD) over the first ESL, wherein the ILD comprises a second discontinuity, the second discontinuity substantially aligned with the first discontinuity;
- a liner on first sidewalls of the first discontinuity and second discontinuity;
- a second via electrically coupled with the first via, the second via comprising a fill metal between the liner on the first sidewalls;
- a capacitor on at least a portion of the fill metal, the capacitor comprising:
- a first bottom electrode in contact with the fill metal;
- a second bottom electrode on the first bottom electrode;
- a dielectric layer comprising a ferroelectric or a paraelectric material on the second bottom electrode;
- a first top electrode on the dielectric layer;
- and
- a second top electrode on the first top electrode, wherein the structure further comprises:
- a second ESL on the ILD, the second ESL adjacent to the first bottom electrode;
- an encapsulation material on second sidewalls of the capacitor;
- and
- a metal contact on the second top electrode, wherein the apparatus further comprises:
- a plate line coupled with the metal contact;
- a word line coupled with the gate contact;
- and
- a bit line coupled with a third via, wherein the third via is coupled with the source contact.
26 more elements
An apparatus comprising:
- a transistor within a ferroelectric cell region, the transistor comprising:
- a source;
- a drain;
- a gate electrode between the source and the drain;
- a drain contact coupled with the drain;
- a source contact coupled with the source;
- a gate contact coupled with the gate electrode;
- and
- a first via coupled with the drain contact, wherein the apparatus further comprises:
- a structure coupled to the first via, the structure comprising:
- an etch stop layer (ESL) with a first discontinuity;
- a first interlayer dielectric (ILD) over the ESL, wherein the first ILD comprises a second discontinuity, the second discontinuity substantially aligned with the first discontinuity;
- a liner on first sidewalls of the first discontinuity and second discontinuity;
- a second via electrically coupled with the first via, the second via comprising a fill metal between the liner on the first sidewalls;
- a capacitor on at least a portion of the fill metal, the capacitor comprising:
- a first bottom electrode in contact with the fill metal;
- a second bottom electrode on the first bottom electrode;
- a non-linear dielectric layer comprising a ferroelectric or a paraelectric material on the second bottom electrode;
- a first top electrode on the non-linear dielectric layer;
- and
- a second top electrode on the first top electrode, wherein the structure further comprises:
- an encapsulation material comprising a first portion on second sidewalls of the capacitor;
- a metal contact on the second top electrode;
- and
- a plate line coupled with the metal contact;
- a word line coupled with the gate contact, wherein the apparatus further comprises:
- a bit line coupled with a third via, wherein the third via is coupled with the source contact;
- and
- a second structure within a logic region, the second structure comprising,
- a fourth via comprising the fill metal within a third discontinuity in the first etch stop layer (ESL) and within a fourth discontinuity in the first ILD;
- and
- and a fifth via within a fifth discontinuity in a second ILD, wherein the fifth discontinuity is substantially aligned and over the fourth discontinuity, and wherein the second ILD is above the first ILD.
29 more elements
A system comprising:
- a processor circuitry to execute one or more instructions;
- a communication interface communicatively coupled to the processor circuitry;
- and
- a memory to store the one or more instructions, wherein the processor circuitry or the memory includes an apparatus comprising:
- a transistor, comprising:
- a source;
- a drain;
- a gate electrode between the source and the drain;
- a drain contact coupled with the drain;
- a source contact coupled with the source;
- a gate contact coupled with the gate electrode;
- and
- a first via coupled with the drain contact, wherein the apparatus further comprises:
- a structure coupled to the first via, the structure comprising:
- a first etch stop layer (ESL) with a first discontinuity;
- a first interlayer dielectric (ILD) over the ESL, wherein the first ILD comprises a second discontinuity, the second discontinuity substantially aligned with the first discontinuity;
- a liner on first sidewalls of the first discontinuity and the second discontinuity;
- a second via electrically coupled with the first via, the second via comprising a fill metal between the liner on the first sidewalls;
- a capacitor on at least a portion of the fill metal, the capacitor comprising:
- a first bottom electrode in contact with the fill metal;
- a second bottom electrode on the first bottom electrode;
- a dielectric layer comprising a ferroelectric or a paraelectric material on the second bottom electrode;
- a first top electrode on the dielectric layer;
- and
- a second top electrode on the first top electrode, wherein the structure furthe comprises:
- a second ESL on the ILD, the second ESL adjacent to the first bottom electrode;
- an encapsulation material on second sidewalls of the capacitor;
- and
- a metal contact on the second top electrode, wherein apparatus further comprises:
- a plate line coupled with the metal contact;
- a word line coupled with the gate contact;
- and
- a bit line coupled with a third via, wherein the third via is coupled with the source contact.
30 more elements
Dependencies are inferred from the claim text.