US 11,641,731 B2Granted

DRAM and manufacturing method therefore

AssigneeWinbond Electronics Corp.

InventorShu-Mei Lee

Life of this patent

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Abstract

A DRAM including following components is provided. A bit line stack structure includes a bit line structure and a hard mask layer. The bit line structure is located on the substrate. The hard mask layer is located on the bit line structure. A dielectric layer is located on the bit line stack structure and has an opening. A contact structure is located on the substrate and includes an active region contact and a capacitor contact. The active region contact is located on the substrate. The top surface of the active region contact is exposed by the opening. The capacitor contact is located in the opening over the active region contact. An isolation layer is located between the hard mask layer and the dielectric layer and between the capacitor contact and the bit line stack structure. An etch stop layer is located between the dielectric layer and the isolation layer.

Claims18

Dependent claims

A method of manufacturing a DRAM, comprising:

providing a substrate;
forming a bit line stack structure on the substrate, wherein the bit line stack structure comprises:
a bit line structure located on the substrate;
and
a hard mask layer located on the bit line structure;
forming an active region contact on the substrate on one side of the bit line stack structure;
conformally forming an isolation material layer on the hard mask layer and the active region contact;
conformally forming an etch stop material layer on the isolation material layer, wherein a material of the etch stop material layer is different from a material of the isolation material layer;
forming a dielectric layer on the etch stop material layer;
forming an opening in the dielectric layer, wherein the opening exposes the etch stop material layer located on a sidewall of the hard mask layer and located above the active region contact;
removing a portion of the etch stop material layer exposed by the opening to form an etch stop layer and to cause the opening to expose the isolation material layer located on the sidewall of the hard mask layer and located on the active region contact;
removing a portion of the isolation material layer located on the active region contact to form an isolation layer and to cause the opening to expose the active region contact;
forming a capacitor contact in the opening, wherein the isolation layer is located between the hard mask layer and the dielectric layer and located between the capacitor contact and the bit line stack structure;
and
forming a capacitor on the capacitor contact, wherein the capacitor comprises:
a lower electrode connected to the capacitor contact;
an upper electrode located on the lower electrode;
and
a capacitor dielectric layer located between the upper electrode and the lower electrode.

16 more elements

A method of manufacturing a DRAM, comprising:

providing a substrate;
forming a bit line stack structure on the substrate, wherein the bit line stack structure comprises:
a bit line structure located on the substrate;
and
a hard mask layer located on the bit line structure;
forming an active region contact on the substrate on one side of the bit line stack structure;
conformally forming an isolation material layer on the hard mask layer and the active region contact;
conformally forming an etch stop material layer on the isolation material layer, wherein a material of the etch stop material layer is different from a material of the isolation material layer;
forming a dielectric layer on the etch stop material layer;
forming an opening in the dielectric layer, wherein the opening exposes the etch stop material layer located on a sidewall of the hard mask layer and located above the active region contact;
removing a portion of the etch stop material layer exposed by the opening to form an etch stop layer and to cause the opening to expose the isolation material layer located on the sidewall of the hard mask layer and located on the active region contact;
removing a portion of the isolation material layer located on the active region contact to form an isolation layer and to cause the opening to expose the active region contact;
and
forming a capacitor contact in the opening, wherein
the method of manufacturing the DRAM further comprises:
conformally forming a barrier material layer on a surface of the opening before forming the capacitor contact;
and
removing the barrier material layer located outside the opening to form a barrier layer, wherein the barrier layer is located between the capacitor contact and the active region contact, and the barrier layer, the capacitor contact, and the dielectric layer are coplanar.

15 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/340,065Filed 6 Jun 2021
Priority: TW 10912086919 Jun 2020
Published: US 2021/0398983 A123 Dec 2021
Granted: 2 May 2023
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

H10B 12/0335
The capacitor extending over the transistor: making a connection between the transistor and the capacitor, e.g. plug
H10B 12/315
Having a storage electrode stacked over the transistor: with the capacitor higher than a bit line
H10B 12/482
Data lines or contacts therefor: bit lines
H10B
Electronic memory devices