Transistor device with (anti)ferroelectric spacer structures

An integrated circuit (IC) device comprising:

• doped source or drain regions of a transistor;
• a channel region of the transistor, the channel region disposed between the doped source or drain regions;
• and
• spacers which each extend over a different respective one of the doped source or drain regions, the spacers comprising a first spacer which comprises:
• a first portion comprising a ferroelectric or anti-ferroelectric material;
• and
• a second portion comprising a material other than the ferroelectric or anti-ferroelectric material, wherein the first portion is offset vertically from the second portion.

A system comprising:

• an integrated circuit (IC) device comprising:
• a transistor structure comprising:
• a fin structure comprising doped source or drain regions, and a channel region between the doped source or drain regions;
• a layer on the channel region, the layer comprising a dielectric material;
• spacers which each extend over a different respective one of the doped source or drain regions, the spacers comprising a first spacer which comprises:
• a first portion comprising a ferroelectric or anti-ferroelectric material;
• and
• a second portion comprising a material other than the ferroelectric or anti-ferroelectric material, wherein the first portion is offset vertically from the second portion;
• and
• a gate electrode which extends over the layer in a region between the spacers;
• and
• a display device coupled to the IC device, the display device to display an image based on a signal communicated with the transistor structure.