Semiconductor memory device and operating method thereof

A semiconductor memory device, comprising:

• a mode register circuit including a plurality of write mode register sets for providing a plurality of setting codes or a plurality of monitoring codes, wherein each of the write mode register sets includes:
• a storing circuit suitable for storing an operational code according to a mode register write command;
• and an output control circuit suitable for outputting the stored operational code in the storing circuit as a corresponding setting code, or inverting the stored operational code in the storing circuit to output a corresponding monitoring code, according to a test mode signal;
• and
• a defect detection circuit suitable for outputting a defect determination signal by detecting any defect in the mode register circuit, based on the plurality of monitoring codes,
• wherein the defect detection circuit includes:
• a first detection circuit suitable for outputting a first detection signal that is enabled when all bits of the monitoring codes become a first logic level;
• a second detection circuit suitable for outputting a second detection signal that is enabled when all bits of the monitoring codes become a second logic level;
• and
• a decision circuit suitable for generating the defect determination signal based on the first detection signal and the second detection signal.

A semiconductor memory device comprising:

• a mode register circuit including a plurality of write mode register sets;
• and
• a defect detection circuit,
• wherein each of the write mode register sets:
• stores a first operational code in response to a first test mode signal and outputs the first operational code as a first monitoring code;
• and
• stores a second operational code in response to a second test mode signal and outputs the second operational code as a second monitoring code,
• wherein the defect detection circuit:
• performs a logical operation on first monitoring codes from the plurality of write mode register sets to generate a first detection signal;
• performs the logical operation on second monitoring codes from the plurality of write mode register sets to generate a second detection signal;
• and
• generates a detect determination signal indicating a defect in any register set of the write mode register sets based on the first and second detection signals.