Integrated circuit device including gate line

An integrated circuit device comprising:

• a plurality of first active areas extending in a first direction on a substrate;
• a plurality of second active areas extending in the first direction on the substrate;
• a first gate line extending in a second direction intersecting with the first direction to intersect with the plurality of first active areas, the first gate line having a first width;
• a second gate line extending in the second direction to intersect with the plurality of second active areas, the second gate line having a second width which is narrower than the first width;
• a third gate line extending in the second direction apart from the second gate line in the second direction, the third gate line having the second width;
• a first gate dielectric layer conformally on all vertical surfaces of the first gate line;
• a first gate spacer conformally on vertical surfaces of the first gate dielectric layer which extend in the second direction;
• and
• a first gate isolation layer between the second gate line and the third gate line, the first gate isolation layer including a face contacting the first gate dielectric layer and the first gate spacer, a width of the face of the gate isolation layer is equal to a width between outer faces of the first gate spacer, the outer faces being opposite one another,
• wherein
• the first gate line comprises a curved surface and comprises a first sidewall and a second sidewall having different curvatures, and
• the first gate isolation layer contacts the second gate line and the third gate line.

An integrated circuit device comprising:

• a substrate including a cell area, where a static random access memory (SRAM) cell is located, and a peri area where a peripheral circuit configured to operate the SRAM cell is located;
• a first upper gate line extending in one direction in the cell area;
• a first upper gate dielectric layer conformally on all vertical surfaces of the first upper gate line;
• a first upper gate spacer conformally on vertical surfaces of the first upper gate dielectric layer;
• a first lower gate line extending in the one direction in the cell area apart from the first upper gate line in the one direction;
• a first gate isolation layer between the first upper gate line and the first lower gate line, the first gate isolation layer including a face contacting the first upper gate dielectric layer and the upper first gate spacer, a width of the face of the first gate isolation layer is equal to a width between outer faces of the first upper gate spacer, the outer faces being opposite one another;
• a second upper gate line extending in one direction in the peri area;
• a second lower gate line extending in the one direction in the peri area apart from the second upper gate line in the one direction;
• and
• a second gate isolation layer between the second upper gate line and the second lower gate line,
• wherein
• the first gate isolation layer contacts the first upper gate line and the first lower gate line,
• the second gate isolation layer is apart from the second upper gate line and the second lower gate line, and
• each of the second upper gate line and the second lower gate line comprises a concave sidewall.