Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device, comprising:

• providing a substrate in which a main area including a first cell area and a first peripheral area, and an edge area including a second cell area and a second peripheral area are defined;
• sequentially forming a mold layer, a supporter layer, a mask layer, an anti-reflective coating layer, and a preliminary pattern layer on the substrate;
• exposing the preliminary pattern layer to light to form a first pattern and a second pattern on the anti-reflective coating layer of the first cell area and the second cell area, respectively;
• forming an etch stop layer on the second pattern, the etch stop layer not being formed on the main area;
• and
• etching the mask layer using the etch stop layer and the first pattern to form a hole pattern in the mold layer and the supporter layer of the first cell area.

A method of manufacturing a semiconductor device, comprising:

• providing a substrate in which a main area including a first cell area and a first peripheral area, and an edge area including a second cell area and a second peripheral area are defined;
• sequentially forming a mold layer, a supporter layer, a mask layer, an anti-reflective coating layer, and a preliminary pattern layer on the substrate;
• exposing the preliminary pattern layer to light to simultaneously form a first pattern and a second pattern on the anti-reflective coating layer of the first cell area and the second cell area, respectively;
• forming an etch stop layer on the second pattern, the etch stop layer not being formed on the main area;
• forming a hole pattern in the first cell area using the etch stop layer and the first pattern to extend through the mold layer, the supporter layer and the mask layer, the hole pattern not being formed on the first peripheral area, the second cell area and the second peripheral area,
• forming a lower electrode in the hole pattern;
• exposing an upper surface of the supporter layer, such that upper ends of the supporter layer on the first cell area, an upper end of the supporter layer on the first peripheral area, an upper end of the supporter layer on the second cell area, and an upper end of the supporter layer on the second peripheral area are at substantially a same level;
• forming a supporter mask layer on the supporter layer;
• patterning the supporter mask layer to form a supporter mask pattern;
• forming a supporter opening using the supporter mask pattern to extend through the supporter layer;
• removing the mold layer;
• forming a capacitor dielectric layer on the lower electrode;
• forming an upper electrode on the capacitor dielectric layer;
• forming an interlayer insulating layer on the upper electrode;
• and
• planarizing the interlayer insulating layer.