Ramp generator providing high resolution fine gain including fractional divider with delta-sigma modulator

An imaging system, comprising:

• a pixel array including a plurality of pixel circuits arranged in a plurality of rows and a plurality of columns, wherein each one of the pixel circuits is coupled to generate an image signal in response to incident light;
• a control circuitry coupled to the pixel array to control operation of the pixel array;
• and
• a readout circuitry coupled to the pixel array to read out the image data from the plurality of pixel cells through bitlines, wherein the readout circuitry comprises
• column comparators coupled to the bitlines to receive the image data from the plurality of pixels and further coupled to receive a ramp signal during an analog to digital conversion operation to provide a digital representation of the image data in response;
• and
• a ramp generator coupled to generate the ramp signal with high resolution fine gain in response to an adjustable fractional divider ratio K, the ramp generator comprising:
• a current mirror having a first path coupled to conduct a capacitor current, and a second path coupled to conduct an integrator current responsive to the capacitor current;
• a first switched capacitor circuit and a second switched capacitor circuit coupled to the first path;
• a fractional divider circuit coupled to receive a clock signal to generate in response to the fractional divider ratio K a switched capacitor control signal that oscillates between first and second states to control the first and second switched capacitor circuits, wherein the first switched capacitor circuit is coupled to be charged by the capacitor current and the second switched capacitor circuit is coupled to be discharged in response to each first state of the switched capacitor control signal, wherein the first switched capacitor circuit is coupled to be discharged and the second switched capacitor circuit is coupled to be charged by the capacitor current in response to each second state of the switched capacitor control signal;
• and
• an integrator coupled to the second path to generate the ramp signal in response to the integrator current.