US 11,594,268 B2 · Memory device deserializer circuit with a reduced form factor

Abstract

A memory device including a memory array operatively coupled to an array data bus and a deserializer circuit operatively coupled with the array data bus. The deserializer circuit includes a first ring counter including a first set of flip-flops to sequentially output a set of rising edge clock signals based on a reference clock input and a second ring counter portion including a second set of flip-flop circuits to sequentially output a set of falling edge clock signals based on the reference clock input. A rising data circuit portion of the deserializer circuit includes a set of flip-flops that each receive a rising data portion from a respective latch circuit in response to a rising edge clock signal. A falling data circuit portion of the deserializer circuit includes a set of flip-flops that each receive a falling data portion from a respective latch circuit in response to a falling edge clock signal. The third set of flip-flops outputs the set of rising data portions and the fourth set of flip-flop circuits outputs the set of falling data portions to generate a synchronized data stream to output to the array data bus in response to a common clock signal.

Claims20

Dependent claims

A memory device comprising:

a memory array operatively coupled to an array data bus;
and
a deserializer circuit operatively coupled with the array data bus, the deserializer circuit comprising:
a first ring counter portion comprising a first set of flip-flop circuits to sequentially output a set of rising edge clock signals based on a reference clock input;
a second ring counter portion comprising a second set of flip-flop circuits to sequentially output a set of falling edge clock signals based on the reference clock input;
a rising data circuit portion comprising:
a third set of flip-flop circuits, wherein each of the third set of flip-flop circuits receives a rising data portion of a set of rising data portions in response to a rising edge clock signal of the set of rising edge clock signals;
and
a falling data circuit portion comprising:
a fourth set of flip-flop circuits, wherein each of the fourth set of flip-flop circuits receives a falling data portion of a set of falling data portions in response to a falling edge clock signal of the set of falling edge clock signals;
wherein the third set of flip-flop circuits outputs the set of rising data portions and the fourth set of flip-flop circuits outputs the set of falling data portions to generate a synchronized data stream to output to the array data bus in response to a common clock signal.

8 more elements

A deserializer circuit of a memory device, the deserializer circuit comprising:

a ring counter portion comprising a first set of flip-flop circuits to sequentially output a set of rising edge clock signals based on a reference clock input;
a first rising data circuit portion coupled to the ring counter portion, the first rising data circuit portion comprising:
a second set of flip-flop circuits, wherein each of the second set of flip-flop circuits receives a rising data portion of a first set of rising data portions of a first serial input stream in response to a first respective rising edge clock signal of the set of rising edge clock signals;
and
a second rising data circuit portion coupled to the ring counter portion, the second rising data portion comprising:
a third set of flip-flop circuits, wherein each of the third set of flip-flop circuits receives a rising data portion of a second set of rising data portions of a second serial input stream in response to a second respective rising edge clock signal of the set of rising edge clock signals.

3 more elements

A memory device comprising:

a memory array operatively coupled to an array data bus;
and
a deserializer circuit operatively coupled with the array data bus, the deserializer circuit comprising:
a ring counter portion comprising a first set of flip-flop circuits to sequentially output a set of rising edge clock signals based on a reference clock input;
a first rising data circuit portion coupled to the ring counter portion, the first rising data circuit portion comprising:
a second set of flip-flop circuits, wherein each of the second set of flip-flop circuits receives a rising data portion of a first set of rising data portions of a first serial input stream in response to a first respective rising edge clock signal of the set of rising edge clock signals;
and
a second rising data circuit portion coupled to the ring counter portion, the second rising data portion comprising:
a third set of flip-flop circuits, wherein each of the third set of flip-flop circuits receives a rising data portion of a second set of rising data portions of a second serial input stream in response to a second respective rising edge clock signal of the set of rising edge clock signals.

6 more elements

Dependencies are inferred from the claim text.

Memory device deserializer circuit with a reduced form factor

Life of this patent

Memory device deserializer circuit with a reduced form factor

Life of this patent

Abstract

Claims20