US 11,570,400 B2 · Systems and methods for asymmetric image splitter clock generation

Abstract

Described herein are systems and methods that provide for asymmetric image splitter image stream applications. In one embodiment, a system supporting image multi-streaming comprises an asymmetric image splitter engine that splits super-frame image streams into two or more image streams and a fractional clock divider circuit. The fractional clock divider may comprise a digital feedback control loop and a one-bit sigma delta modulator. The fractional clock divider circuit may provide compatible display clock frequencies for each of the two or more image streams. When a multi-image stream comprises the two image streams, the asymmetric image splitter engine adjusts a vertical asymmetry of a first image stream with a shortest height to same height as a second image stream by adding vertical padding to the first image stream. The super-frame image streams may comprise image streams from video, LIDAR, radar, or other sensors.

Claims18

Dependent claims

A system supporting image multi-streaming comprising:

an asymmetric image splitter engine that splits super-frame image streams into two or more image streams;
and
a fractional clock divider circuit comprising a digital feedback control loop,
wherein the fractional clock divider circuit provides compatible display clock frequencies for each of the two or more image streams without an incorporation of one or more phase-lock-loop (PLL) oscillators.

1 more element

Dependencies are inferred from the claim text.

Facts

Application

16/381,267Filed 11 Apr 2019 · us provisional application

Priority

13 Jun 2018

Published

US 2019/0387197 A119 Dec 2019

Granted

31 Jan 2023

Term ends

Not estimatedThe source records don’t support an estimate.

Classification24 codes

H04N 7/12
Television systems: systems in which the television signal is transmitted via one channel or a plurality of parallel channels, the bandwidth of…
G06F 1/04
Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00: generating or distributing clock signals or signals derived directly therefrom
H03K 23/48
Gating or clocking signals applied to all stages, i.e. synchronous counters: with a base or radix other than a power of two
H03M 3/428
The quantiser being a multiple bit one: with lower resolution, e.g. single bit, feedback

Systems and methods for asymmetric image splitter clock generation

Life of this patent

Systems and methods for asymmetric image splitter clock generation

Life of this patent

Abstract

Claims18