Time-to-digital converter calibration

A digital phase-locked loop (DPLL), comprising:

• a time-to-digital converter (TDC) configured to provide a phase error signal that indicates a phase difference between a reference signal and a feedback signal;
• a frequency divider configured to perform frequency division on an output signal of the DPLL to generate the feedback signal;
• a delta-sigma modulator (DSM) configured to provide a test signal associated with calibrating the TDC, wherein the test signal represents a quantization error of the DSM;
• and
• a TDC calibration component configured to calibrate the TDC while the DPLL is operating in a phase-locked state by applying a gain adjustment factor to the TDC, wherein the gain adjustment factor is based on the phase error signal and the test signal.

A method, comprising;

• causing, during operation in a time-to-digital converter (TDC) calibration mode, a predetermined percentage of a quantization error of a delta-sigma modulator (DSM) of a digital phase-locked loop (DPLL) to be included in a phase error signal provided by a TDC of the DPLL;
• calibrating, during operation in the TDC calibration mode, the TDC by applying a gain adjustment factor to the TDC,
• wherein the gain adjustment factor is based on a test signal representing the quantization error of the DSM and the phase error signal including the predetermined percentage of the quantization error;
• determining that a gain of the TDC matches an ideal gain of the TDC;
• freezing the gain of the TDC and entering a normal operation mode based on determining that the gain of the TDC matches the ideal gain of the TDC;
• and
• preventing, during operation in the normal operation mode, the quantization error from being included in the phase error signal provided by the TDC.