Digital resolver decoder with hardware filter and rectifier

A processor having an integrated resolver decoder circuit, the processor comprising:

• an analog-to-digital converter (ADC) circuit configured to:
• generate first digital samples by converting a first analog signal from a sine winding of a resolver, and
• generate second digital samples by converting a second analog signal from a cosine winding of the resolver, the first analog signal and the second analog signal being generated by exciting an input winding of the resolver with a sine wave signal;
• a first tapped delay line (TDL) filter coupled to the ADC circuit and configured to calculate a first weighted sum of the first digital samples over a pre-determined period of time;
• a second TDL filter coupled to the ADC circuit and configured to calculate a second weighted sum of the second digital samples over the pre-determined period of time;
• a rectifier configured to generate a first output and a second output by adjusting a first sign of the first weighted sum and a second sign of the second weighted sum, respectively;
• and
• a central processing unit (CPU) coupled to the rectifier.

A method of operating a resolver decoder circuit, the method comprising:

• converting a first analog signal from a sine winding of a resolver into first data samples;
• converting a second analog signal from a cosine winding of the resolver into second data samples;
• calculating a first weighted sum of the first data samples over a pre-determined period of time;
• calculating a second weighted sum of the second data samples over the pre-determined period of time;
• adjusting a first sign of the first weighted sum and a second sign of the second weighted sum based on a location of the pre-determined period of time within a cycle of a sine wave signal;
• after the adjusting, dividing the first weighted sum by the second weighted sum to obtain a value;
• and
• determining an arctangent of the value to obtain an angle.