US 11,561,765 B2Granted

Scalable input/output system and techniques to transmit data between domains without a central processor

AssigneeIntel Corporation

InventorsJohn Howard, Steven B. McGowan, Krzysztof Perycz

Life of this patent

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Abstract

An apparatus for managing input/output (I/O) data may include a streaming I/O controller to receive data from a load/store domain component and output the data as first streaming data of a first data type comprising a first data movement type and first data format type. The apparatus may also include at least one accelerator coupled to the streaming I/O controller to receive the first streaming data, transform the first streaming data to second streaming data having a second data type different than the first data type, and output the second streaming data. In addition, the apparatus may include a streaming interconnect to conduct the second data to a peer device configured to receive data of the second data type.

Claims22

Dependent claims

At least one computer readable storage device comprising computer readable instructions that, when executed, cause at least one processor associated with a cloud based service to at least:

access first video data from a first data storage location, the first video data having a first format;
cause a first accelerator associated with the cloud based service to transform a portion of the first video data to a second video data portion having a second format different from the first format;
cause the second video data portion to be stored;
cause a second accelerator associated with the cloud based service to transform at least the second video data portion into at least one first data segment formatted to stream to a first device;
and
cause a third accelerator associated with the cloud based service to transform at least the second video data portion into at least one second data segment formatted to stream to a second device, the at least one second data segment in a different format than the at least one first data segment, the at least one first data segment and the at least one second data segment to be streamable concurrently.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/384,496Filed 23 Jul 2021 · continuation
Priority: 7 Nov 2018
Published: US 2022/0050662 A117 Feb 2022
Granted: 24 Jan 2023
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

G06F 5/065
For changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor:…
G06F 5/14
Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations: for…
G06F 13/1673
Details of memory controller: using buffers
G06F 13/28
For access to input/output bus: using burst mode transfer, e.g. direct memory access DMA, cycle steal

Family

PCT/US2013/078006Parent of this continuation · filed 27 Dec 2013
Application16/182,932Parent of this continuation · filed 7 Nov 2018
US 10,127,012 B2Parent of this continuation · filed 13 Nov 2018
Application16/819,772Parent of this continuation · filed 16 Mar 2020
US 10,592,205 B2Parent of this continuation · filed 17 Mar 2020
US 2022/0050662 A1Pre-grant publication · published 17 Feb 2022
US 11,074,042 B2Parent of this continuation
Application15/039,934Parent of this continuation
US 2017/0212724 A1Published application
US 2019/0073194 A1Published application
US 2020/0218505 A1Published application
US 11,561,765 B2This patent

From the US filing history. Foreign family members aren’t listed.