Method and arrangement for ensuring valid data at a second stage of a digital register circuit

An integrated circuit, comprising at least one register circuit for temporarily storing a digital value obtained from an output of a circuit element preceding said at least one register circuit in the integrated circuit, the at least one register circuit comprising:

• the data input for receiving said digital value for temporary storage,
• a data input for outputting the temporarily stored a digital value,
• a triggering event input for receiving a triggering signal, a triggering edge of which defines an allowable time limit before which a digital value must appear at said data input to become temporarily stored, and
• on the data propagation path between said data input and data output a sequence of a first pulse-enabled subregister stage and second pulse-enabled subregister stage;
• wherein said at least one register comprises, between said first and second pulse-enabled subregister stages, a timing event stage configured to use an internal digital value from the first pulse-enabled subregister stage and information of the changing moment of said digital value at the data input in relation to said allowable time limit to ensure passing a valid internal digital value to the second pulse-enabled subregister stage,
• wherein said timing event stage is configured to output a timing event observation signal at an output of said at least one register circuit as an indicator of said digital value at said data input having changed within a time window that begins at said allowable time limit and is shorter than one cycle of said triggering signal, and
• wherein said timing event stage comprises:
• a timing event logic configured to selectively invert the internal digital value obtained from the first pulse-enabled subregister stage and
• a timing event controller configured to detect any change of said digital value at said data input within a time window that begins at said allowable time limit and is shorter than a half cycle of said triggering signal, and configured to make said timing event logic effect said selective inverting as a response to such change having been detected.

A method for temporarily storing a digital value obtained from an output of a preceding circuit element and for making such a temporarily stored digital value available for a subsequent circuit element at a controlled moment of time, the method comprising:

• receiving said digital value through a data input for temporary storage, and
• receiving a triggering signal, a triggering edge of which defines an allowable time limit before which a digital value must be available at said data input to become available for said subsequent circuit element,
• using, between first and second pulse-enabled subregister stages, an internal digital value from the first pulse-enabled subregister stage and information of the changing moment of said digital value at the data input in relation to said allowable time limit to ensure passing a valid internal digital value to the second pulse-enabled subregister stage,
• using said second pulse-enabled subregister stage for making said valid internal digital value available for said subsequent circuit element, and
• outputting a timing event observation signal as an indicator of said digital value at said data input having changed within a time window that begins at said allowable time limit and is shorter than one cycle of said triggering signal;
• wherein the method comprises:
• using a timing event logic to selectively invert the internal digital value obtained from the first pulse-enabled subregister stage and
• using a timing event controller configured to detect any change of said digital value at said data input within a time window that begins at said allowable time limit and is shorter than a half cycle of said triggering signal, and configured to make said timing event logic effect said selective inverting as a response to such change having been detected.