Variable clock divider
AssigneeMicron Technology, Inc.
InventorYutaka Uemura
Life of this patent
Estimating the term…
Abstract
Disclosed herein is an apparatus that includes a first shift register circuit including a plurality of first latch circuits coupled in series, and a second shift register circuit including a plurality of second latch circuits coupled in series. The first and second shift register circuits are cyclically coupled. Each of the first latch circuits is configured to perform the latch operation in synchronization with a rise edge of a first clock signal. Each of the second latch circuits is configured to perform the latch operation in synchronization with a fall edge of a first clock signal when a first selection signal is in a first state. One or more first latch circuits and one or more second latch circuits are configured to be bypassed when a second selection signal indicates a predetermined value.
Claims20
An apparatus comprising:
- a plurality of latch circuits coupled cyclically, each of the latch circuits being configured to perform a latch operation in synchronization with a first clock signal;
- and
- a clock generating circuit configured to generate a second clock signal,
- wherein the latch circuits are divided into:
- a first group having two or more latch circuits coupled in series, each of the latch circuits included in the first group being configured to perform the latch operation in synchronization with one of rise and fall edges of the first clock signal;
- and
- a second group having two or more latch circuits coupled in series, each of the latch circuits included in the second group being configured to perform the latch operation in synchronization with the rise edge of the first clock signal when a first selection signal is in a first state and perform a latch operation in synchronization with the fall edge of the first clock signal when the first selection signal is in a second state, and
- wherein the clock generating circuit is configured to change the second clock signal from a first logic level to a second logic level in response to a first output signal of the first group, and change the second clock signal from the second logic level to the first logic level in response to a second output signal of the second group.
An apparatus comprising:
- a first shift register circuit including a plurality of first latch circuits coupled in series and configured to perform a latch operation in synchronization with a first clock signal;
- a second shift register circuit including a plurality of second latch circuits coupled in series and configured to perform a latch operation in synchronization with the first clock signal;
- and
- a clock generating circuit configured to generate a second clock signal,
- wherein the first and second shift register circuits are cyclically coupled,
- wherein each of the first latch circuits is configured to perform the latch operation in synchronization with one of rise and fall edges of the first clock signal,
- wherein each of the second latch circuits is configured to perform a latch operation in synchronization with other of the rise and fall edges of the first clock signal when the first selection signal is in a first state, and
- wherein the clock generating circuit is configured to change the second clock signal from a first logic level to a second logic level in response to one of output signals from the first latch circuits, and change the second clock signal from the second logic level to the first logic level in response to one of output signals from the second latch circuits.
An apparatus comprising:
- a first shift register circuit including a plurality of first latch circuits coupled in series;
- and
- a second shift register circuit including a plurality of second latch circuits coupled in series,
- wherein the first and second shift register circuits are cyclically coupled,
- wherein each of the first latch circuits is configured to perform the latch operation in synchronization with a rise edge of a first clock signal,
- wherein each of the second latch circuits is configured to perform the latch operation in synchronization with a fall edge of a first clock signal when a first selection signal is in a first state,
- wherein one or more first latch circuits and one or more second latch circuits are configured to be bypassed when a second selection signal indicates a predetermined value.
Dependencies are inferred from the claim text.