US 11,451,731 B2 · Counter circuit and image sensor including the same

Abstract

An image sensor includes a pixel sensor outputting an analog sampling signal; a sampling unit comparing the sampling signal and a ramp signal, and outputting a comparison signal that is time-axis length information; and a counter counting a length of the comparison signal based on a clock signal and first and second complement control signals. The counter includes an AND gate ANDing the comparison signal and the clock signal; and a counting unit triggered at a falling edge of the AND gate output to output a count value. The counting unit includes a complement operation controller storing an inverted count value that is an inversion of the count value in response to the first complement control signal, and outputting the inverted count value in response to the second complement control signal; and a D-flip-flop that is set or reset depending on the inverted count value, and outputs the count value.

Claims19

Dependent claims

An image sensor, comprising:

a pixel sensor configured to sense an incident light and to output an analog sampling signal;
a sampling unit configured to compare the sampling signal and a ramp signal, and to output a comparison signal that is time-axis length information;
and
a counter configured to count a length of the comparison signal in response to a clock signal, a first complement control signal, and a second complement control signal, wherein:
the counter includes:
a first AND gate configured to perform an AND operation on the comparison signal and the clock signal;
and
a first counting unit triggered at a falling edge of an output of the first AND gate to output a first count value, and
the first counting unit includes:
a first complement operation controller configured to store an inverted first count value corresponding to an inverted version of the first count value in response to the first complement control signal, and to output the inverted first count value in response to the second complement control signal;
and
a first D-flip-flop that is set or reset depending on the inverted first count value output from the first complement operation controller, and configured to output the first count value.

9 more elements

A counter circuit that counts a high period or a low period of an input signal using a clock signal, the counter circuit comprising:

a first AND gate configured to perform an AND operation on the input signal and the clock signal;
and
a ripple counter including a first counting unit and a second counting unit that are triggered by an output of the first AND gate to count a length of the input signal, the first counting unit toggling a first count bit, and the second counting unit toggling a second count bit that is an upper bit of the first count bit,
wherein, when a division control signal is activated, the first counting unit latches and outputs an inverted second count bit that is an inverted version of the second count bit toggled by the second counting unit.

1 more element

Dependencies are inferred from the claim text.

Counter circuit and image sensor including the same

Life of this patent

Counter circuit and image sensor including the same

Life of this patent

Abstract

Claims19