Signal-to-noise and interference ratio (SNAIR) aware analog to digital converter (ADC)-based receiver and a method thereof

A Signal to Noise And Interference Ratio (SNAIR) aware-Analog to Digital Converter (ADC)-based-receiver, wherein the SNAIR aware-ADC based receiver comprises:

• an analog front end (AFE) configured for recovering an input data signal with a bit error rate (BER) below a target BER;
• a sampler communicatively coupled to the AFE, wherein the sampler is configured for receiving the input data signal from the AFE, sampling the received input data signal, and distributing the sampled input data signal to a sub-analog-to-digital converter (SADC) array;
• the SADC array communicatively coupled to the sampler, and wherein the SADC array comprises an array of identical analog-to-digital converters (ADCs) configured for converting the sampled input data signal into a digital data signal, and wherein the ADCs are time-interleaved for achieving a predetermined sampling frequency;
• a digital signal processing (DSP) unit communicatively coupled to the SADC array, wherein the DSP unit uses a baud rate sampling scheme, and wherein the DSP unit comprises:
• a feed forward equalizer (FFE) configured to remove residual inter-symbol interference (ISI) by multiplying a delayed version of the digital data signal with Htap values;
• and
• one or more-taps decision feedback equalizer (DFE) configured to remove remaining ISI caused by a first y previous symbols where y is the number of DFE taps using (n−1) decision levels at each of ‘n’ possible previous symbols, where n is the number of levels used in a PAM scheme;
• a baud rate sampling system communicatively coupled to the DSP unit, wherein the baud rate sampling system is configured to generate a plurality of error signals and data signals using an output of the one or more-taps decision feedback equalizer (DFE);
• a clock data recovery (CDR) system communicatively coupled to the baud rate sampling system, wherein the CDR system is configured to process the generated plurality of error signals and data signals for aligning a main sample clock with the input data signal and maximize a corresponding eye opening;
• an eye quality measurement system communicatively coupled to an output of the DSP unit, wherein the eye quality measurement system is configured to measure an eye quality of the input data signal by determining a margin estimation value and corresponding outer eye measurements associated with an eye;
• and
• a digital control communicatively coupled to each of the AFE, the sampler, the SADC array, the DSP unit, and the eye quality measurement system, wherein the digital control is operated by instructions from the DSP unit and is configured for:
• auto-calibrating each of the AFE, the sampler, the SADC array, and the eye quality measurement system;
• and
• optimizing performance of the AFE to recover the input data signal at the target BER.