Sample and hold circuit and method

A sample and hold method performed with a sample and hold circuit, the method comprising:

• receiving a first input signal with top electrodes of first capacitors in a sample phase, and receiving a second input signal with all bottom electrode(s) of at least a part of the first capacitors in the sample phase;
• stopping receiving the first input signal with the top electrodes of the first capacitors in a hold phase, receiving a first group of reference signals with all bottom electrodes of the first capacitors in the hold phase, and providing a first sample voltage on the top electrodes of the first capacitors by charge redistribution in the hold phase;
• receiving the second input signal with top electrodes of second capacitors in the sample phase, and receiving the first input signal with all bottom electrode(s) of at least a part of the second capacitors in the sample phase;
• and
• stopping receiving the second input signal with the top electrodes of the second capacitors in the hold phase, receiving a second group of reference signals with all bottom electrodes of the second capacitors in the hold phase, and providing a second sample voltage on the top electrodes of the second capacitors by charge redistribution in the hold phase.

A sample and hold method performed with a sample and hold circuit, the method comprising:

• receiving a first input signal with top electrodes of first capacitors in a sample phase, and receiving a first reference signal with all bottom electrode(s) of at least a part of the first capacitors in the sample phase;
• stopping receiving the first input signal with the top electrodes of the first capacitors in a hold phase, receiving a first group of reference signals with all bottom electrodes of the first capacitors in the hold phase, and providing a first sample voltage on the top electrodes of the first capacitors by charge redistribution in the hold phase;
• receiving a second input signal with top electrodes of second capacitors in the sample phase, and receiving a second reference signal with all bottom electrode(s) of at least a part of the second capacitors in the sample phase, wherein the second reference signal is different from the first reference signal;
• and
• stopping receiving the second input signal with the top electrodes of the second capacitors in the hold phase, receiving a second group of reference signals with all bottom electrodes of the second capacitors in the hold phase, and providing a second sample voltage on the top electrodes of the second capacitors by charge redistribution in the hold phase.