Metastabile state detection device and method, and ADC circuit

An ADC circuit comprising:

• a metastable state detection device, wherein the metastable state detection device includes:
• a delay unit which is configured to receive a synchronization signal and delay the synchronization signal;
• a first flip-flop unit including a first clock input terminal, a first data input terminal and a first data output terminal, wherein the first clock input terminal is configured to receive a clock signal;
• the first data input terminal is connected to the delay unit and is configured to receive the delayed synchronization signal;
• a second flip-flop unit including a second clock input terminal, a second data input terminal and a second data output terminal, wherein the second clock input terminal is respectively connected to the delay unit and the first data input terminal and is configured to receive the delayed synchronization signal;
• the second data input terminal is connected to the first clock input terminal and is configured to receive a clock signal;
• the second data output terminal is configured to output a target clock signal that is synchronized with the delayed synchronization signal;
• a processing module connected to the second data output terminal, which is configured to receive the target clock signal and detect a metastable state of the first flip-flop unit according to the target clock signal.

A metastable detection method, wherein the detection method is applicable to a metastable state detection device, and wherein the metastable state detection device includes a delay unit, a first flip-flop unit, and a second flip-flop unit, wherein a clock input terminal of the first flip-flop unit is connected to a data input terminal of the second flip-flop unit, both of which are configured to receive a clock signal, and wherein a data input terminal of the first flip-flop unit and a clock input terminal of the second flip-flop unit are respectively connected to the delay unit, both of which are configured to receive a delayed synchronization signal;

• wherein the method includes:
• controlling the delay unit to delay the received synchronization signal based on preset delay values;
• recording target clock signals from the second flip-flop unit in correspondence with each of the delay values;
• detecting a metastable state of the first flip-flop unit according to the recorded correspondence relationships between the delay values and the target clock signals.