Pulse width modulator with reduced pulse width

A method, comprising:

• receiving a clock signal with a phase locked loop;
• generating, with the phase locked loop, N phase signals each having different phases from each other and a same period T as the clock signal;
• receiving, with a data delay generator, a data input signal and the phase signals;
• generating, with the data delay generator, N data delay signals each corresponding to the data input signal and delayed in accordance with a respective one of the phase signals;
• receiving a first half of the data delay signals with a first multiplexer stage;
• receiving a second half of the data delay signals with a second multiplexer stage having a same internal delay as the first multiplexer stage;
• and
• generating, with a third multiplexer stage, a data output pulse having a width based on an output of the first multiplexer stage and an output of the second multiplexer stage.

A pulse width modulator, comprising:

• a phase locked loop configured to receive a clock signal having a period T and to generate N phase signals each having the period T of the clock signal and each offset in time from the clock signal by a respective integer number of unit steps, wherein a unit step is a period of time equal to T/N;
• a data delay generator configured to receive a data input signal and to generate, for each phase signal, a respective data delay signal corresponding to the data input signal delayed in accordance with the phase signal;
• a first multiplexer stage configured to receive, as inputs, a first group of N/2 of the data delay signals;
• a second multiplexer stage configured to receive, as inputs, a second group of N/2 of the data delay signals distinct from the first group;
• and
• a third multiplexer stage configured to receive, as inputs, an output of the first multiplexer and an output of the second multiplexer, and to provide a data pulse having a rising edge triggered by either the output of the first multiplexer or the output of the second multiplexer stage and a falling edge triggered by the output of either the first multiplexer stage or the second multiplexer stage.