Majority logic gate based flip-flop with non-linear polar material

An apparatus comprising:

• a first latch comprising a first data input, a first data output, and a first clock input, wherein the first latch a first capacitor with non-linear polar material;
• a second latch comprising a second data input, a second data output, and a second clock input, wherein the second latch comprises a second capacitor with non-linear polar material, and wherein the first data output is coupled to the second data input;
• and
• an inverting logic gate coupled to the first clock input and the second clock input.

A system comprising:

• a processor circuitry to execute one or more instructions;
• a communication interface communicatively coupled to the processor circuitry;
• and
• a memory coupled to the processor circuitry, wherein the memory is to store the one or more instructions, and wherein the processor circuitry comprises a flip-flop which includes:
• a first latch comprising a first data input, a first data output, and a first clock input, wherein the first latch a first capacitor with non-linear polar material;
• a second latch comprising a second data input, a second data output, and a second clock input, wherein the second latch comprises a second capacitor with non-linear polar material, and wherein the first data output is coupled to the second data input;
• and
• an inverting logic gate coupled to the first clock input and the second clock input.